Cache coherency in a multi-processor system

• US 20040078528A1
• Filed: 07/31/2003
• Published: 04/22/2004
• Est. Priority Date: 07/31/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lasserre, Serge, Chauvel, Gerard, Kuusela, Maija, DʼInverno, Dominique
• Granted Patent: US 6,996,683 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/0253 Garbage collection, i.e. reclamation of unreferenced memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

A system comprises a first processor having cache memory, a second processor having cache memory and a coherence buffer that can be enabled and disabled by the first processor. The system also comprises a memory subsystem coupled to the first and second processors. For a write transaction originating from the first processor, the first processor enables the second processor'"'"'s coherence buffer, and information associated with the first processor'"'"'s write transaction is stored in the second processor'"'"'s coherence buffer to maintain data coherency between the first and second processors.

Claims

6-1. The system of claim 1 wherein the first processor enables the first processor'"'"'s coherence buffer upon originating a write transaction to an area of shared memory in the memory subsystem.

9. A cache coherency method usable in a multi-processor system, comprising:

when a first processor originates a write transaction to shared data, enabling a second processor'"'"'s coherence buffer, and storing information associated with the first processor'"'"'s write transaction in the second processor'"'"'s coherence buffer to maintain data coherency between the first and second processors; and

when the second processor originates a write transaction to shared data, sending a write exception to the first processor to cause the first processor to write data into cache local to the first processor.

10. The method of claim 9 wherein the information comprises an address associated with the write transaction originated by the first processor and the method further comprises invalidating a line in the second processor'"'"'s cache corresponding to the address.

11. The method of claim 9 wherein the information comprises a data value being written by the write transaction originated by the first processor and the method further comprises writing the data value to cache memory in the second processor.

12. The method of claim 9 wherein the first processor disables the coherence buffer in the second processor after completing the write transaction originated by the first processor.