Fault-tolerant synchronisation device for a real-time computer network

• US 20040078614A1
• Filed: 07/02/2003
• Published: 04/22/2004
• Est. Priority Date: 01/16/2001
• Status: Active Grant

• Current Assignee: Thales SA
• Original Assignee: Thales SA
• Inventors: Toillon, Patrice, Colas, Gerard
• Granted Patent: US 7,509,513 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/1679 at clock signal level
• CPC Class Codes: G06F 11/18 using passive fault-masking of the redundant circuits error detection by comparing the output of redundant processing systems with continued operation after detection of the error G06F11/165

Abstract

The invention enables fault-tolerant synchronization of real-time equipment connected to a computer network of several tens of meters with an option of including or not including such equipment in the synchronization device. It provides global scheduling of the real-time computer platform in the form of minor and major cycles in order to reduce latency during sensor acquisition, the associated calculation and preparation of output to the actuator in an integrated modular avionic (IMA) architecture. In order to do this, it uses a synchronization bus separate from the data transfer network and circuits interfacing with this specific bus for processing the local real-time clocks in each piece of equipment in a fault-tolerant, decentralized manner.

Claims

1. A device for synchronizing local real-time clocks (112, 212, 222) of computer equipment connected to a data transfer bus (41) comprising electronic circuits (711, 712, 721, 722) for generating synchronization pulses (A_x, B_x, A_y, B_y), counting circuits (91, 92) for generating the local real-time clock (112, 212, 222) and exchanging the pulses (A_x, B_x, A_y, B_y) with the other synchronization entities (113, 213, 223), time voting circuits (81, 82) for resynchronizing the counting circuits (91, 92), characterized in that the pulses (A_x, B_x, A_y, B_y) are conveyed by a specific synchronization bus (61).

2. The device as claimed in claim 1, characterized in that it further includes power supplies (95, 96) separate from the other synchronization entities.

3. The synchronization device as claimed in one of the preceding claims, characterized in that the exchanges on the channels A_x, B_x, A_y, B_y are formed in synchronization pulse (Sync pulse) and in synchronization type coding (Sync type).

4. The synchronization device as claimed in one of the preceding claims, characterized in that the electronic circuits (711, 712, 721, 722) generate pulses (A_x, B_x, A_y, B_y) on differential lines with dominant and recessive states.

5. The synchronization device as claimed in claim 4, characterized in that the electronic circuits (711, 712, 721, 722) are of the CAN network bidirectional driver type.

6. The synchronization device as claimed in one of the preceding claims, characterized in that the time voting of the pulses (A_x, B_x, A_y, B_y) in the logic circuits (81, 82) is quadruplex majority voting by eliminating the pairs (A_x or B_x) and (A_y or B_y) originating from the same synchronization unit SU_x, SU_y.

7. The synchronization device as claimed in one of the preceding claims, characterized in that the synchronization of the equipment of the computer platform is achieved in the form of minor and major cycles of multiple periods.

8. The synchronization device as claimed in one of the preceding claims, characterized in that the ratio of the major cycle period to that of the minor cycle is between 2 and 10000.

9. The synchronization device as claimed in one of the preceding claims, characterized in that a piece of equipment (11, 21, 22) may or may not be placed in synchronization without disrupting the other pieces of equipment of the platform that have already been synchronized with each other.

10. Computer equipment including a synchronization device as claimed in one of the preceding claims.

11. A synchronization method for computer equipment comprising four operating states (Sync disable, Wait, Out of sync, In sync), by exchange of synchronization pulses, characterized in that the pulses (A_x, B_x, A_y, B_y) are conveyed by a specific synchronization bus (61).

12. The synchronization method as claimed in claim 11, characterized in that a transition from the (Out of sync) state to an (In sync) state is triggered by the expiration of a waiting time or the sending of a synchronization initialization sequence (Init sync) or of a synchronization sequence of a first type (Start_miF) or of a second type (Start_MAF).

13. The synchronization method as claimed in claim 11, characterized in that a transition from the (In sync) state to an (Out of sync) state is triggered by the arrival of unexpected synchronization sequences or by a first negative vote on four signals (A_x, B_x, A_y, B_y) or a second negative vote on three codes (Init_sync, Start_miF, Start_MAF).

14. The synchronization method as claimed in claim 13, characterized in that the first and second votes are of the same type.

15. The synchronization method as claimed in claim 12 or claim 13, characterized in that the synchronization sequences have a minor cycle and a major cycle of multiple periods.

16. The synchronization method as claimed in claim 15, characterized in that the ratio of the major cycle period to that of the minor cycle is between 2 and 10000.