Event processing system

• US 20040078724A1
• Filed: 06/26/2002
• Published: 04/22/2004
• Est. Priority Date: 06/26/2002
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rogers, Gregory Dennis, Robbert, George Harold, Keller, S. Brandon
• Application Number:
  US10/180,044
• Publication Number:
  US 20040078724A1
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Techniques are disclosed for processing events, such as errors, in an event processing computer system. For example, an event processor may receive an indication of an event (such as an error), identify a priority of the event, and determine whether an action is associated with the priority of the event. If an action is associated with the priority of the event, the action may be performed. The action may, for example, include outputting a message associated with the event to an output location. A user of the system may specify which actions the event processor is to perform for events of various priorities. For example, the user may indicate that messages should only be output for events having specified priorities. The user may specify such actions, and other parameters of the event processor, using configuration information which is distinct from the event processor.

Claims

1. A computer-implemented method comprising steps of:

(A) receiving an indication of an error;

(B) identifying a priority of the error;

(C) determining whether at least one action is associated with the priority of the error;

(D) identifying the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error; and

(E) performing the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error.

2. The method of claim 1, wherein the step (A) comprises a step of receiving the error indication from a circuit design analysis tool, and wherein the error indication comprises an indication of an error generated by the circuit design analysis tool when analyzing a circuit design.

3. The method of claim 1, further comprising a step of:

(F) identifying a type of the error; and

wherein the step (B) comprises a step of;

(B)(1) identifying the priority of the error based on the type of the error.

4. The method of claim 3, wherein the step (B)(1) comprises steps of:

(B)(1)(a) identifying a plurality of mappings between a plurality of error types and a plurality of error priorities;

(B)(1)(b) identifying one of the plurality of mappings which maps the type of the error to a mapped error priority; and

(B)(1)(c) identifying the mapped error priority as the priority of the error.

5. The method of claim 3, further comprising steps of:

(G) identifying an identifier of the error;

(H) determining whether an override priority is associated with the identifier of the error; and

wherein the step (B) further comprises a step of;

(B)(2) identifying the override priority as the priority of the error if it is determined that an override priority is associated with the identifier of the error.

6. The method of claim 1, wherein the step (C) comprises a step of determining whether an output action is associated with the priority of the error, wherein the step (D) comprises steps of:

(D)(1) identifying at least one output location associated with the error;

(D)(2) identifying an error message associated with the error; and

wherein the step (E) comprises a step of;

(E)(1) outputting the error message associated with the error to the at least one output location associated with the error only if it is determined that the output action is associated with the priority of the error.

7. The method of claim 6, wherein the error indication comprises a data structure including an indicated error message, and wherein the step (D)(2) comprises a step of identifying the indicated error message as the error message associated with the error.

8. The method of claim 6, wherein the step (D)(1) comprises steps of:

(D)(1)(a) identifying a plurality of mappings between a plurality of error priorities and a plurality of output locations;

(D)(1)(b) identifying one of the plurality of mappings which maps the priority of the error to at least one mapped output location; and

(D)(1)(c) identifying the mapped output location as the at least one output location associated with the error.

9. The method of claim 6, further comprising steps of:

(F) identifying an identifier of the error;

(G) determining whether an output suppression action is associated with the identifier of the error; and

wherein the step (E)(1) comprises a step of outputting the error message associated with the error to the at least one output location associated with the error only if it is determined that the output action is associated with the priority of the error and it is determined that the output suppression action is not associated with the identifier of the error.

10. The method of claim 6, further comprising steps of:

(F) identifying an identifier of the error;

(G) determining whether an output enablement action is associated with the identifier of the error; and

wherein the step (E)(1) comprises a step of outputting the error message associated with the error to the at least one output location associated with the error if it is determined either that the output action is associated with the priority of the error or that the output enablement action is associated with the identifier of the error.

11. The method of claim 1, wherein the step (C) comprises steps of:

(C)(1) identifying a plurality of mappings between a plurality of error priorities and a plurality of error actions;

(C)(2) identifying one of the plurality of mappings corresponding to the priority of the error; and

(C)(3) determining whether the identified mapping maps the priority of the error to at least one action.

12. The method of claim 1, wherein the step (D) comprises steps of:

(D)(1) identifying at least one mapped error action to which the identified mapping maps the priority of the error; and

(D)(2) identifying the at least one mapped error action as the at least one action associated with the priority of the error.

13. The method of claim 1, wherein the step (D) comprises steps of:

(D)(1) identifying an error counter limit associated with the error;

(D)(2) identifying an error counter value associated with the error;

(D)(3) determining whether the error counter value is greater than the error counter limit; and

wherein the step (E) comprises a step of performing the at least one action associated with the priority if it is determined that the error counter value is not greater than the error counter limit.

14. The method of claim 13, further comprising a step of:

(D)(4) incrementing the error counter value.

15. The method of claim 13, wherein the step (D)(1) comprises steps of:

(D)(1)(a) identifying a plurality of mappings between a plurality of error types and a plurality of error counter limits;

(D)(1)(b) identifying one of the plurality of mappings which maps the identified error type to at least one mapped error counter limit; and

(D)(1)(c) identifying the mapped error counter limit as the error counter limit.

16. The method of claim 13, wherein the step (D)(1) comprises steps of:

(D)(1)(a) identifying an identifier of the error;

(D)(1)(b) identifying a mapped error counter limit associated with the identifier of the error; and

(D)(1)(c) identifying the mapped error counter limit as the error counter limit.

17. The method of claim 1, wherein the step (C) comprises a step of determining whether a process termination action is associated with the priority, and wherein the step (E) comprises a step of terminating a process associated with the method if it is determined that the process termination action is associated with the priority.

18. The method of claim 17, wherein the process associated with the method comprises a computer-implemented process performed by a circuit design analysis tool to analysis a circuit design.

19. The method of claim 1, further comprising steps of:

(F) identifying an identifier of the error;

(G) determining whether a suppression action is associated with the identifier of the error; and

wherein the step (E) comprises a step of performing the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error and it is determined that the suppression action is not associated with the identifier of the error.

20. The method of claim 1, further comprising steps of:

(F) identifying an identifier of the error;

(G) determining whether an enablement action is associated with the identifier of the error; and

wherein the step (E) comprises a step of performing the at least one action associated with the priority of the error if it is determined either that at least one action is associated with the priority of the error or that the enablement action is associated with the identifier of the error.

21. A computer system comprising:

receiving means for receiving an indication of an error;

priority identification means for identifying a priority of the error;

action determination means for determining whether at least one action is associated with the priority of the error;

action identification means for identifying the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error; and

action performance means for performing the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error.

22. The system of claim 21, wherein the receiving means comprises means for receiving the error indication from a circuit design analysis tool, and wherein the error indication comprises an indication of an error generated by the circuit design analysis tool when analysis a circuit design.

23. The system of claim 21, further comprising:

type identification means for identifying a type of the error; and

wherein the priority identification means comprises means for identifying the priority of the error based on the type of the error.

24. The system of claim 23, further comprising:

a plurality of mappings between a plurality of error types and a plurality of error priorities; and

wherein the priority identification means further comprises;

means for identifying one of the plurality of mappings which maps the type of the error to a mapped error priority; and

means for identifying the mapped error priority as the priority of the error.

25. The system of claim 23, further comprising:

means for identifying an identifier of the error;

means for determining whether an override priority is associated with the identifier of the error; and

wherein the priority identification means further comprises means for identifying the override priority as the priority of the error if it is determined that an override priority is associated with the identifier of the error.

26. The system of claim 21, wherein the action determination means comprises means for determining whether an output action is associated with the priority of the error, wherein the action identification means comprises:

means for identifying at least one output location associated with the error;

means for identifying an error message associated with the error; and

wherein the action performance means comprises;

means for outputting the error message associated with the error to the at least one output location associated with the error only if it is determined that the output action is associated with the priority of the error.

27. The system of claim 26, wherein the error indication comprises a data structure including an indicated error message, and wherein the action identification means comprises means for identifying the indicated error message as the error message associated with the error.

28. The system of claim 26, further comprising:

a plurality of mappings between a plurality of error priorities and a plurality of output locations; and

wherein the action identification means further comprises;

means for identifying one of the plurality of mappings which maps the priority of the error to at least one mapped output location; and

means for identifying the mapped output location as the at least one output location associated with the error.

29. The system of claim 26, further comprising:

means for identifying an identifier of the error;

means for determining whether an output suppression action is associated with the identifier of the error; and

wherein the means for outputting the error message comprises means for outputting the error message associated with the error to the at least one output location associated with the error only if it is determined that the output action is associated with the priority of the error and it is determined that the output suppression action is not associated with the identifier of the error.

30. The system of claim 26, further comprising:

means for identifying an identifier of the error;

means for determining whether an output enablement action is associated with the identifier of the error; and

wherein the means for outputting the error message comprises means for outputting the error message associated with the error to the at least one output location associated with the error if it is determined either that the output action is associated with the priority of the error or that the output enablement action is associated with the identifier of the error.

31. The system of claim 21, further comprising:

a plurality of mappings between a plurality of error priorities and a plurality of error actions; and

wherein the action determination means comprises;

means for identifying one of the plurality of mappings corresponding to the priority of the error; and

means for determining whether the identified mapping maps the priority of the error to at least one action.

32. The system of claim 31, wherein the action identification means comprises:

means for identifying at least one mapped error action to which the identified mapping maps the priority of the error; and

means for identifying the at least one mapped error action as the at least one action associated with the priority of the error.

33. The system of claim 21, wherein the action identification means comprises:

means for identifying an error counter limit associated with the error;

means for identifying an error counter value associated with the error;

means for determining whether the error counter value is greater than the error counter limit; and

wherein the action performance means comprises means for performing the at least one action associated with the priority if it is determined that the error counter value is not greater than the error counter limit.

34. The system of claim 33, further comprising:

means for incrementing the error counter value.

35. The system of claim 33, further comprising:

a plurality of mappings between a plurality of error types and a plurality of error counter limits; and

wherein the action identification means further comprises;

means for identifying one of the plurality of mappings which maps the identified error type to at least one mapped error counter limit; and

means for identifying the mapped error counter limit as the error counter limit.

36. The system of claim 33, wherein the means for identifying an error counter limit comprises:

means for identifying an identifier of the error;

means for identifying a mapped error counter limit associated with the identifier of the error; and

means for identifying the mapped error counter limit as the error counter limit.

37. The system of claim 21, wherein the action determination means comprises means for determining whether a process termination action is associated with the priority, and wherein the action performance means comprises means for terminating a process associated with the method if it is determined that the process termination action is associated with the priority.

38. The system of claim 37, wherein the process associated with the method comprises a computer-implemented process performed by a circuit design analysis tool to analysis a circuit design.

39. The system of claim 21, further comprising:

means for identifying an identifier of the error;

means for determining whether a suppression action is associated with the identifier of the error; and

wherein the action performance means comprises means for performing the at least one action associated with the priority of the error if it is determined that at least one action is associated with the priority of the error and it is determined that the suppression action is not associated with the identifier of the error.

40. The system of claim 21, further comprising:

means for identifying an identifier of the error;

means for determining whether an enablement action is associated with the identifier of the error; and

wherein the action performance means comprises means for performing the at least one action associated with the priority of the error if it is determined either that at least one action is associated with the priority of the error or that the enablement action is associated with the identifier of the error.

41. A computer-implemented method comprising steps of:

(A) receiving an indication of an event associated with a message suitable for output to a user through an output device;

(B) identifying a priority of the event;

(C) determining whether the message should be output to the user through the output device based on the priority of the event; and

(D) outputting the message to the user through the output device if it is determined that the message should be output to the user through the output device.

42. The method of claim 41, wherein the step (A) comprises a step of receiving the event indication from a circuit design analysis tool, and wherein the event indication comprises an indication of an event generated by the circuit design analysis tool when analyzing a circuit design.

43. The method of claim 41, further comprising a step of:

(E) identifying a type of the event; and

wherein the step (B) comprises a step of;

(B)(1) identifying the priority of the event based on the type of the event.

44. The method of claim 43, wherein the step (B)(1) comprises steps of:

(B)(1)(a) identifying a plurality of mappings between a plurality of event types and a plurality of event priorities;

(B)(1)(b) identifying one of the plurality of mappings which maps the type of the event to a mapped event priority; and

(B)(1)(c) identifying the mapped event priority as the priority of the event.

45. The method of claim 43, further comprising steps of:

(F) identifying an identifier of the error;

(G) determining whether an override priority is associated with the identifier of the error; and

wherein the step (B) further comprises a step of;

(B)(2) identifying the override priority as the priority of the error if it is determined that an override priority is associated with the identifier of the error.

46. The method of claim 41, wherein the step (C) comprises steps of:

(C)(1) identifying a plurality of mappings between a plurality of event priorities and a plurality of output locations;

(C)(2) identifying one of the plurality of mappings which corresponds to the priority of the event; and

(C)(3) determining that the message should be output to the user through the output device if the identified one of the plurality of mappings maps the priority of the event to an output location.

47. A computer system comprising:

receiving means for receiving an indication of an event associated with a message suitable for output to a user through an output device;

priority identification means for identifying a priority of the event;

output determination means for determining whether the message should be output to the user through the output device based on the priority of the event; and

output means for outputting the message to the user through the output device if it is determined that the message should be output to the user through the output device.

48. The system of claim 47, wherein the receiving means comprises means for receiving the event indication from a circuit design analysis tool, and wherein the event indication comprises an indication of an event generated by the circuit design analysis tool when analyzing a circuit design.

49. The system of claim 47, further comprising:

event identification means for identifying a type of the event; and

wherein the priority identification means comprises;

means for identifying the priority of the event based on the type of the event.

50. The system of claim 49, further comprising:

a plurality of mappings between a plurality of event types and a plurality of event priorities; and

wherein the priority identification means further comprises;

means for identifying one of the plurality of mappings which maps the type of the event to a mapped event priority; and

means for identifying the mapped event priority as the priority of the event.

51. The system of claim 49, further comprising:

means for identifying an identifier of the error;

means for determining whether an override priority is associated with the identifier of the error; and

wherein the priority identification means further comprises means for identifying the override priority as the priority of the error if it is determined that an override priority is associated with the identifier of the error.

52. The system of claim 47, wherein the output determination means comprises:

means for identifying a plurality of mappings between a plurality of event priorities and a plurality of output locations;

means for identifying one of the plurality of mappings which corresponds to the priority of the event; and

means for determining that the message should be output to the user through the output device if the identified one of the plurality of mappings maps the priority of the event to an output location.

53. A computer system comprising:

a plurality of priority-action mappings between a plurality of event priorities and a plurality of event actions; and

a software program comprising computer program instructions for;

receiving an indication of an event associated with a message suitable for output to an output location;

identifying a priority of the event;

determining whether an action is associated with the event based on the plurality of priority-action mappings;

identifying the action associated with the event if it is determined that an action is associated with the event; and

performing the action associated with the event if it is determined that an action is associated with the event;

wherein the plurality of priority-action mappings do not comprise a part of the computer program instructions.

54. The system of claim 53, wherein the event indication comprises an indication of an event generated by a circuit design analysis tool when analyzing a circuit design.

55. The system of claim 53, further comprising:

a plurality of type-priority mappings between a plurality of event types and a plurality of event priorities, wherein the plurality of type-priority mappings do not comprise a part of the computer program instructions; and

wherein the software program further comprises computer program instructions for;

receiving a type of the error;

identifying one of the plurality of type-priority mappings which maps the type of the error to a mapped error priority; and

identifying the mapped error priority as the priority of the error.

56. The system of claim 53, further comprising:

a plurality of priority-location mappings between the plurality of event priorities and a plurality of output locations, wherein the plurality of priority-location mappings do not comprise a part of the computer program instructions; and

wherein the software program further comprises computer program instructions for;

identifying one of the plurality of priority-location mappings which maps the priority of the error to a mapped output location; and

outputting the message to the mapped output location if it is determined that an action is associated with the event.

57. The system of claim 56, further comprising:

a plurality of type-limit mappings between the plurality of event types and a plurality of event counter limits, wherein the plurality of type-limit mappings do not comprise a part of the computer program instructions; and

wherein the software program further comprises computer program instructions for;

identifying one of the plurality of type-limit mappings which maps the type of the event to a mapped counter limit; and

identifying the mapped counter limit as a counter limited associated with the event.

58. The system of claim 53, further comprising:

a plurality of priority-action mappings between the plurality of event priorities and a plurality of event actions, wherein the plurality of priority-action mappings do not comprise a part of the computer program instructions; and

wherein the software program further comprises computer program instructions for;

identifying one of the plurality of priority-action mappings which maps the priority of the event to a mapped event action;

identifying the mapped event action as the action associated with the event.