Method for operating a processor-controlled system

• US 20040078731A1
• Filed: 04/07/2003
• Published: 04/22/2004
• Est. Priority Date: 10/06/2000
• Status: Active Grant

• Current Assignee: Vitesco Technologies GmbH (Continental AG)
• Original Assignee: Conti Temic Microelectronic GmbH (Continental AG)
• Inventors: Pohlmann, Roger, Becher, Alwin, Bertelshofer, Peter
• Granted Patent: US 7,174,483 B2
• Time in Patent Office: Days
• US Class Current: 714/55
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

1. Method for operating a system controlled by a processor.

2.1 A simple and economical method for monitoring an especially safety critical system is suggested.

2.2 For this purpose, an integrated monitoring unit independent of the processor is integrated together with the processor in an integrated circuit; a watchdog unit for preventing measures that influence the system must be cyclically reset by the integrated monitoring unit.

2.3 Method for operating a safety critical operating function, controlled by a processor, of a motor vehicle.

Claims

1. Method for operating a system controlled by a processor (1), characterized in that, for monitoring the functional condition of the processor (1) an integrated monitoring unit (6) independent of the processor (1) is integrated together with the processor (1) in an integrated circuit (8), and in that a watchdog unit (5) for preventing measures that influence the system must be cyclically reset by the integrated monitoring unit (6).

2. Method according to claim 1, characterized in that the integrated monitoring unit (6) is tested during the initialization of the system by the processor (1).

3. Method according to claim 1 or 2, characterized in that the functional condition of the processor (1) is monitored by the monitoring unit (6) until it is switched off.

4. Method according to claim 3, characterized in that the integrated monitoring unit (6) can be switched off by the processor (1).

5. Method according to one of the claims 1 to 4, characterized in that the integrated monitoring unit (6) is connected with the functional units (3, 4) of the processor (1) via a bus system (2).

6. Method according to one of the claims 1 to 5, characterized in that the watchdog unit (5) must be reset within a time window by the integrated monitoring unit (6).

7. Method according to one of the claims 1 to 6, characterized in that the watchdog unit (5) is integrated in the integrated circuit (8).

8. Method according to one of the claims 1 to 7, characterized in that a resetting of the watchdog unit (5) is carried out in accordance with an inquiry directed from the integrated monitoring unit (6) to the processor (1).

9. Method according to claim 8, characterized in that the inquiry to the processor (1) is carried out via an inquiry value prescribed by the integrated monitoring unit (6), according to which a certain algorithm is executed in the processor (1), the result of which is compared with an expected value of the integrated monitoring unit (6).

10. Method according to one of the claims 1 to 9, characterized in that a resetting of the processor (1) is carried out upon the absence of a resetting of the watchdog unit (5).

11. Method according to one of the claims 1 to 10, characterized in that the system is brought into a system condition independent of the processor (1) upon the absence of a resetting of the watchdog unit (5).