Integrated thin film capacitor/inductor/interconnect system and method

• US 20040080021A1
• Filed: 10/15/2003
• Published: 04/29/2004
• Est. Priority Date: 09/21/2001
• Status: Active Grant

• Current Assignee: Ultrasource, Inc. (Michigan) (Vishay Intertechnology Incorporated)
• Original Assignee: Michael D. Casper, William B. Mraz
• Inventors: Casper, Michael D., Mraz, William B.
• Granted Patent: US 6,998,696 B2
• Time in Patent Office: Days
• US Class Current: 257/528
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 23/15 Ceramic or glass substrates H01L23/142, H01L23/145, H01L23/147 take precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/016 Thin-film circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/19011 including integrated passive components
• CPC Class Codes: H01Q 21/061 Two dimensional planar arrays
• CPC Class Codes: H05K 1/16 incorporating printed electric components, e.g. printed resistor, capacitor, inductor
• CPC Class Codes: H05K 1/162 incorporating printed capacitors
• CPC Class Codes: H05K 1/165 incorporating printed inductors
• CPC Class Codes: H05K 2201/0179 Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
• CPC Class Codes: H05K 2201/0317 Thin film conductor layer; Thin film passive component
• CPC Class Codes: H05K 2201/09763 Printed component having superposed conductors, but integrated in one circuit layer
• CPC Class Codes: H05K 3/002 by liquid chemical etching
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/467 Adding a circuit layer by thin film methods H05K3/4647 takes precedence

Abstract

A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

Claims

1. A thin film capacitor/inductor/interconnect method comprising:

(1) thinly metalizing a substrate with a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness of less than or equal to 1.5 microns;

(2) applying/imaging photoresist and etching to form metal patterns on said substrate for lower capacitor electrodes and interconnect;

(3) applying a thin dielectric layer to said metal patterns;

(4) applying/imaging photoresist and etching to form contact holes in said dielectric layer and optionally selectively patterning said dielectric layer;

(5) metalizing said substrate to make contact with said lower capacitor electrodes and interconnect;

(6) applying/imaging photoresist and etching to form patterns for upper capacitor electrodes, inductors, and/or interconnect conductors;

(7) optionally forming resistor elements by applying/imaging photoresist and etching a resistor layer on said substrate;

wherein

said upper conducting layer is approximately 0.25 microns thick.

2. The thin film hybrid substrate method of claim 1, wherein said lower adhesive layer is approximately 0.03 to 0.05 microns thick.

3. The thin film hybrid substrate method of claim 1, wherein said lower adhesive layer comprises chrome.

4. The thin film hybrid substrate method of claim 1, wherein said lower adhesive layer comprises titanium.

5. The thin film hybrid substrate method of claim 1, wherein said lower adhesive layer comprises titanium-tungsten.

6. The thin film hybrid substrate method of claim 1, wherein said upper conducting layer comprises silver.

7. The thin film hybrid substrate method of claim 1, wherein said upper conducting layer comprises aluminum.

8. The thin film hybrid substrate method of claim 1, wherein said upper conducting layer comprises gold.

9. The thin film hybrid substrate method of claim 1, wherein said upper conducting layer comprises copper.

10. The thin film hybrid substrate method of claim 1, wherein said lower electrode and interconnect layer further comprises silver.

11. The thin film hybrid substrate method of claim 1, wherein said lower electrode and interconnect layer further comprises aluminum.

12. The thin film hybrid substrate method of claim 1, wherein said lower electrode and interconnect layer further comprises gold.

13. The thin film hybrid substrate method of claim 1, wherein said lower electrode and interconnect layer further comprises copper.

14. The thin film hybrid substrate method of claim 1, wherein said lower electrode and interconnect layer is selected from the group consisting of tantalum, tungsten, titanium, nickel, molybdenum, platinum, palladium, and chromium.

15. The thin film hybrid substrate method of claim 1, wherein said dielectric layer is selectively patterned.

16. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises silicon nitride.

17. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises silicon dioxide.

18. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises silicon oxynitride.

19. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises aluminum oxide.

20. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises tantalum pentoxide.

21. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises a ferroelectric material.

22. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is BaTiO₃.

23. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is SrTiO₃.

24. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is PbZrO₃.

25. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is PbTiO₃.

26. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is LiNbO₃.

27. The thin film hybrid substrate method of claim 21, wherein said ferroelectric material is Bi₁₄Ti₃O₁₂.

28. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises polyimide.

29. The thin film hybrid substrate method of claim 1, wherein said dielectric layer further comprises benzocyclobutene.

30. The thin film hybrid substrate method of claim 1, wherein said substrate material is selected from the group consisting of alumina, beryllium oxide, fused silica, aluminum nitride, sapphire, ferrite, diamond, LTCC, and glass.

31. The capacitor/inductor/interconnect product of the thin film fabrication method comprising:

(1) thinly metalizing a substrate with a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness of less than or equal to 1.5 microns;

(2) applying/imaging photoresist and etching to form metal patterns on said substrate for lower capacitor electrodes and interconnect;

(3) applying a thin dielectric layer to said metal patterns;

(4) applying/imaging photoresist and etching to form contact holes in said dielectric layer and optionally selectively patterning said dielectric layer;

(5) metalizing said substrate to make contact with said lower capacitor electrodes and interconnect;

(6) applying/imaging photoresist and etching to form patterns for upper capacitor electrodes, inductors, and/or interconnect conductors;

(7) optionally forming resistor elements by applying/imaging photoresist and etching a resistor layer on said substrate;

wherein

said upper conducting layer is approximately 0.25 microns thick.

32. The capacitor/inductor/interconnect product of claim 31, wherein said lower adhesive layer is approximately 0.03 to 0.05 microns thick.

33. The capacitor/inductor/interconnect product of claim 31, wherein said lower adhesive layer comprises chrome.

34. The capacitor/inductor/interconnect product of claim 31, wherein said lower adhesive layer comprises titanium.

35. The capacitor/inductor/interconnect product of claim 31, wherein said lower adhesive layer comprises titanium-tungsten.

36. The capacitor/inductor/interconnect product of claim 31, wherein said upper conducting layer comprises silver.

37. The capacitor/inductor/interconnect product of claim 31, wherein said upper conducting layer comprises aluminum.

38. The capacitor/inductor/interconnect product of claim 31, wherein said upper conducting layer comprises gold.

39. The capacitor/inductor/interconnect product of claim 31, wherein said upper conducting layer comprises copper.

40. The capacitor/inductor/interconnect product of claim 31, wherein said lower electrode and interconnect layer further comprises silver.

41. The capacitor/inductor/interconnect product of claim 31, wherein said lower electrode and interconnect layer further comprises aluminum.

42. The capacitor/inductor/interconnect product of claim 31, wherein said lower electrode and interconnect layer further comprises gold.

43. The capacitor/inductor/interconnect product of claim 31, wherein said lower electrode and interconnect layer further comprises copper.

44. The capacitor/inductor/interconnect product of claim 31, wherein said lower electrode and interconnect layer is selected from the group consisting of tantalum, tungsten, titanium, nickel, molybdenum, platinum, palladium, and chromium.

45. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer is selectively patterned.

46. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises silicon nitride.

47. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises silicon dioxide.

48. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises silicon oxynitride.

49. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises aluminum oxide.

50. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises tantalum pentoxide.

51. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises a ferroelectric material.

52. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is BaTiO₃.

53. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is SrTiO₃.

54. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is PbZrO₃.

55. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is PbTiO₃.

56. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is LiNbO₃.

57. The capacitor/inductor/interconnect product of claim 51, wherein said ferroelectric material is Bi₁₄Ti₃Ol₂.

58. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises polyimide.

59. The capacitor/inductor/interconnect product of claim 31, wherein said dielectric layer further comprises benzocyclobutene.

60. The capacitor/inductor/interconnect product of claim 31, wherein said substrate material is selected from the group consisting of alumina, beryllium oxide, fused silica, aluminum nitride, sapphire, ferrite, diamond, LTCC, and glass.

61. A power supply bypass/decoupling/filter network system fabricated using array elements comprising integrated capacitors, inductors, and/or interconnects formed on a thin film hybrid substrate system comprising:

(a) a thin film hybrid substrate;

(b) a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness less than or equal to 1.5 microns.

(c) a dielectric layer deposited on top of the said patterned lower electrode and interconnect layer; and

(d) an upper electrode layer formed on said dielectric layer;

wherein

said upper conducting layer is approximately 0.25 microns thick.

63. The phased antenna array system of claim 62, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 61.

65. The phased antenna array system of claim 64, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 61.

67. The phased antenna array system of claim 66, wherein said array elements further comprise an inductor/capacitor bypass/decoupling/filter network fabricated using said integrated capacitors, inductors, and/or interconnects of claim 61.

62. A phased antenna array system fabricated using array elements comprising integrated capacitors, inductors, and/or interconnects formed on a thin film hybrid substrate system comprising:

(a) a thin film hybrid substrate;

(b) a lower electrode and interconnect layer formed on said thin film hybrid substrate, said layer further comprising a lower adhesive layer and an upper conducting layer having a sum total thickness less than or equal to 1.5 microns.

(c) a dielectric layer deposited on top of the said patterned lower electrode and interconnect layer; and

(d) an upper electrode layer formed on said dielectric layer;

wherein

said upper conducting layer is approximately 0.25 microns thick.

64. The phased antenna array system of claim 62, wherein said array elements are active.

66. The phased antenna array system of claim 62, wherein said array elements are passive.