Circuit substrate and fabrication method thereof

• US 20040080052A1
• Filed: 07/28/2003
• Published: 04/29/2004
• Est. Priority Date: 10/24/2002
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: ASE Material Inc. (ASE Group), Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chao, Shin-Hua, Hung, Chih-Pin, Ou, In-De, Lin, Kuang-Hua, Chen, Chia-Shang
• Granted Patent: US 7,060,595 B2
• Time in Patent Office: Days
• US Class Current: 257/774
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/115 Via connections; Lands around holes or via connections H05K1/112 takes precedence
• CPC Class Codes: H05K 2201/09509 Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 2201/09536 Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/09645 Patterning on via walls; Plural lands around one hole
• CPC Class Codes: H05K 3/043 by using a moving tool for milling or cutting the conductive material
• CPC Class Codes: H05K 3/403 Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.

Claims

1. A circuit substrate, comprising:

a board having a plurality of conductive traces layers and insulating layers, and a via formed in the board;

a plurality of metal layers formed on an inner wall of the via, wherein each of the metal layers electrically connects to said corresponding conductive traces layer respectively; and

an insulator formed in the via to electrically isolate from each of the metal layers.

2. The circuit substrate of claim 1, further comprising a plurality of via lands disposed on the board and at the periphery of the via.

3. The circuit substrate of claim 2, wherein each of the via lands is disposed correspondingly to each of the metal layers.

4. The circuit substrate of claim 1, wherein the insulator is positioned between the metal layers.

5. The circuit substrate of claim 1, wherein the via is a through hole.

6. The circuit substrate of claim 1, wherein the via is a buried via.

7. The circuit substrate of claim 1, wherein the via is a blind via.

8. The circuit substrate of claim 1, wherein the material of the metal layers is copper.

9. The circuit substrate of claim 1, wherein the material of the insulator is epoxy.

10. The circuit substrate of claim 1, wherein the material of the insulator is ink.

11. The circuit substrate of claim 1, wherein the board comprises a plurality of insulating layers and conductive traces layers, and the insulating layers are interlaced with the conductive traces layers.

12. The circuit substrate of claim 2, wherein the via land is made of copper.

13. A fabrication method of a circuit substrate, comprising:

providing a board;

forming a via in the board;

forming a metal layer on an inner wall of the via;

cutting the via to form a cutting street to separate the metal layer into a plurality of separated metal layers; and

filling an insulator in the via and the cutting street.

14. The fabrication method of a circuit substrate of claim 13, further comprising:

forming a via land on the board and at the periphery of the via.

15. The fabrication method of a circuit substrate of claim 14, wherein cutting the via further separates the via land into a plurality of separated via lands.

16. The fabrication method of a circuit substrate of claim 13, wherein the via is a through hole.

17. The fabrication method of a circuit substrate of claim 13, wherein the via is a buried via.

18. The fabrication method of a circuit substrate of claim 13, wherein the via is a blind via.

19. The fabrication method of a circuit substrate of claim 13, wherein the material of the metal layer is copper.

20. The fabrication method of a circuit substrate of claim 13, wherein the material of the insulator layer is epoxy.

21. The fabrication method of a circuit substrate of claim 13, wherein the material of the insulator layer is ink.

22. The fabrication method of a circuit substrate of claim 13, wherein the board comprises a plurality of insulating layers and conductive traces layers, and the insulating layers are interlaced with the conductive traces layers.

23. The fabrication method of a circuit substrate of claim 13, wherein forming the metal layer on the inner wall of the via comprises:

forming an activated film on the inner wall of the via by electro-less plating; and

forming a metal film on the activated film by plating.

24. The fabrication method of a circuit substrate of claim 23, wherein the activated film comprises a conductive polymer film.

25. The fabrication method of a circuit substrate of claim 13, wherein cutting the via comprises mechanical drilling.

26. The fabrication method of a circuit substrate of claim 13, wherein cutting the via comprises laser ablation.

27. The fabrication method of a circuit substrate of claim 13, wherein cutting the via comprises photochemical reaction.

28. The fabrication method of a circuit substrate of claim 13, wherein cutting the via comprises plasma etching.