Bidirectional port with clock channel used for synchronization

• US 20040080338A1
• Filed: 10/21/2003
• Published: 04/29/2004
• Est. Priority Date: 06/28/2001
• Status: Active Grant

• Current Assignee: Aaron K. Martin, Matthew B. Haycock, Stephen R. Mooney
• Original Assignee: Aaron K. Martin, Matthew B. Haycock, Stephen R. Mooney
• Inventors: Mooney, Stephen R., Martin, Aaron K., Haycock, Matthew B.
• Granted Patent: US 6,803,790 B2
• Time in Patent Office: Days
• US Class Current: 326/82
• CPC Class Codes: G06F 13/4077 Precharging or discharging

Abstract

A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Claims

1. An electronic device having digital electronic communication capability, the electronic device comprising:

a data transceiver;

a clock driver with an enable input node;

a control circuit to drive the enable input node when the data transceiver is initialized; and

a clock receiver circuit having a clock detection circuit to detect the presence of an incoming clock signal;

wherein the control circuit comprises an initialization circuit to initialize the data transceiver.

2. The electronic device of claim 1 wherein the data transceiver comprises:

a voltage mode output driver having an output node; and

a data receiver having an input node coupled to the output node of the voltage mode driver.

3. The electronic device of claim 1 wherein the data transceiver comprises:

a current mode output driver having a differential output node; and

a data receiver having a differential input node coupled to the differential output node of the current mode driver.

4. The electronic device of claim 1 wherein the initialization circuit comprises an impedance control circuit.

5. The electronic device of claim 4 wherein the control circuit is operative to enable the clock driver when the impedance control circuit has initialized an impedance of the data transceiver.

6. The electronic device of claim 5 wherein:

the data transceiver includes a voltage mode driver having an output impedance; and

the impedance initialized by the impedance control circuit is the output impedance of the voltage mode driver.

7. The electronic device of claim 5 wherein:

the data transceiver includes a current mode driver having at least one termination resistor; and

the impedance initialized by the impedance control circuit is the at least one termination resistor.

8. The electronic device of claim 1 wherein:

the data transceiver includes a variable current source circuit; and

the initialization circuit is operative to initialize the variable current source circuit.

9. The electronic device of claim 1 wherein:

the data transceiver includes a receiver circuit having a variable offset; and

the initialization circuit is operable to initialize the variable offset of the receiver circuit.