Method and circuit for generating time stamp data from an embedded-clock audio data stream and a video clock

• US 20040080671A1
• Filed: 02/04/2003
• Published: 04/29/2004
• Est. Priority Date: 06/14/2002
• Status: Active Grant

• Current Assignee: Koninklijke Philips N.V.
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Sheet, William, Siemens, Duane
• Granted Patent: US 7,283,566 B2
• Time in Patent Office: Days
• US Class Current: 348/473
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/203 Details of error rate determination, e.g. BER, FER or WER
• CPC Class Codes: H04L 1/206 for modulated signals
• CPC Class Codes: H04N 11/042 Codec means
• CPC Class Codes: H04N 21/23614 Multiplexing of additional data and video streams arrangements for simultaneous broadcast of plural pieces of information H04H20/28
• CPC Class Codes: H04N 21/2368 Multiplexing of audio and video streams
• CPC Class Codes: H04N 21/4122 additional display device, e.g. video projector digital output for controlling a plurality of local displays G06F3/1423
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/4348 Demultiplexing of additional data and video streams
• CPC Class Codes: H04N 21/4355 involving reformatting operations of additional data, e.g. HTML pages on a television screen optimising the visualization of content for information retrieval from the Internet G06F16/9577; adaptation of message content in packet-switching networks H04L51/066; media handling at the source in data packet switching networks H04L65/764
• CPC Class Codes: H04N 21/4394 involving operations for analysing the audio stream, e.g. detecting features or characteristics in audio streams arrangements characterised by components specially adapted for monitoring, identification or recognition of audio in broadcast systems H04H60/58
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/602 for digital sound signals

Abstract

In preferred embodiments, a system including a transmitter, a receiver, and a serial link, in which the transmitter is configured to transmit video data, embedded-clock auxiliary data (or auxiliary data derived from embedded-clock auxiliary data), and a video clock over the link to the receiver. The transmitter is configured to extract a sample clock from the auxiliary data without use of a phase-locked loop, and to generate time stamp data in response to the sample clock and the video clock. Typically, the auxiliary data are SPDIF (or other) audio data, and the sample clock changes state in response to codes that occur periodically in the audio data. Other aspects of the invention are a transmitter for use in such a system, a time stamp data generation circuit for use in such a transmitter, and a method for generating time stamp data in response to a stream of embedded-clock auxiliary data and a video clock.

Claims

1. A communication system, including:

a receiver;

a transmitter; and

a serial link between the transmitter and receiver, wherein the transmitter is configured to extract a sample clock from embedded-clock auxiliary data without use of a phase-locked loop, to generate time stamp data in response to a video clock and the sample clock, and to transmit auxiliary data, the time stamp data, and the video clock to the receiver over the link, and

wherein the receiver is configured to generate an auxiliary data clock for the auxiliary data in response to the time stamp data and the video clock.

2. The system of claim 1, wherein the embedded-clock auxiliary data are embedded-clock audio data, and the transmitter is also configured to transmit video data to the receiver over the link.

3. The system of claim 2, wherein the auxiliary data that the transmitter is configured to transmit are audio samples derived from the embedded-clock auxiliary data.

4. The system of claim 3, wherein the transmitter is configured to generate the audio samples by stripping periodically-occurring preambles from the embedded-clock auxiliary data.

5. The system of claim 1, wherein the embedded-clock auxiliary data are embedded-clock audio data having a sample frequency, Fs, the time stamp data are indicative of time stamps, and each of the time stamps is a number of cycles of the video clock in a predetermined audio period.

6. The system of claim 5, wherein the predetermined audio period is P=X/(Y*Fs), where X and Y are integers.

7. The system of claim 1, wherein the transmitter is configured to receive a stream of the embedded-clock auxiliary data, a code occurs periodically in the stream, and the sample clock changes state in response to each occurrence of the code in said stream.

8. The system of claim 1, wherein the transmitter is configured to receive a stream of the embedded-clock auxiliary data, a code occurs periodically in the stream, and the sample clock changes state in response to each Nth occurrence of the code in said stream, where N is an integer.

9. The system of claim 1, wherein the embedded-clock auxiliary data have a sample frequency, Fs, the sample clock signal has a frequency that is at least substantially equal to the sample frequency, Fs and the transmitter includes:

sample clock generation circuitry configured to generate the sample clock in response to the embedded-clock auxiliary data; and

time stamp data generation circuitry coupled to the sample clock generation circuitry and configured to use the sample clock signal as a periodic timing reference to generate the time stamp data.

10. The system of claim 9, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

11. The system of claim 10, wherein Y=128.

12. The system of claim 9, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock and N and Y are integers.

13. The system of claim 9, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate time stamp data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

14. The system of claim 1, wherein the embedded-clock auxiliary data have a sample frequency, Fs, the sample clock signal has a frequency that is at least substantially equal to a predetermined fraction of the sample frequency, Fs, and the transmitter includes:

sample clock generation circuitry configured to generate the sample clock in response to the embedded-clock auxiliary data; and

time stamp data generation circuitry coupled and configured to use the sample clock signal as a periodic timing reference to generate the time stamp data.

15. The system of claim 14, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

16. The system of claim 15, wherein Y=128.

17. The system of claim 14, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock and N and Y are integers.

18. The system of claim 14, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate time stamp data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

19. The system of claim 1, wherein the embedded-clock auxiliary data are SPDIF audio data, and the sample clock changes state in response to occurrences of synchronization codes embedded in the SPDIF audio data.

20. The system of claim 1, wherein the embedded-clock auxiliary data are SPDIF audio data having sample frequency, Fs, and the sample clock changes state in response to each occurrence of a B, M, or W preamble in the SPDIF audio data.

21. The system of claim 20, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

22. The system of claim 20, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock, where N and Y are integers.

23. The system of claim 20, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

24. The system of claim 1, wherein the transmitter is configured to remove jitter from the sample clock, thereby generating a stabilized version of the sample clock, and to generate the time stamp data in response to the video clock and the stabilized version of the sample clock.

25. The system of claim 1, wherein the transmitter is configured to generate a first sequence of cycle time stamp values having a first average value in response to the video clock and the sample clock, and to process the cycle time stamp values to generate the time stamp data, wherein the time stamp data are indicative of a second sequence of cycle time stamp values having an average value at least substantially equal to the first average value, and wherein there is less variation among the cycle time stamps in the second sequence than among the cycle time stamps in the first sequence.

26. A transmitter configured to be coupled to a serial link having at least one video clock channel, said transmitter including:

at least one input coupled to receive embedded-clock auxiliary data;

at least two outputs configured to be coupled to the link, including a clock output configured to be coupled to the video clock channel; and

circuitry, coupled between the outputs and each said input, and configured to extract a sample clock from the embedded-clock auxiliary data without use of a phase-locked loop, to generate time stamp data in response to a video clock and the sample clock, to assert the video clock to the clock output, and to assert auxiliary data and the time stamp data to at least one of the outputs other than the clock output.

27. The transmitter of claim 26, wherein the embedded-clock auxiliary data are embedded-clock audio data.

28. The transmitter of claim 27, wherein the auxiliary data that the circuitry is configured to assert at said at least one of the outputs other than the clock output are audio samples derived from the embedded-clock auxiliary data.

29. The transmitter of claim 28, wherein the circuitry is configured to generate the audio samples by stripping periodically-occurring preambles from the embedded-clock auxiliary data.

30. The transmitter of claim 26, wherein the embedded-clock auxiliary data are embedded-clock audio data having a sample frequency, Fs, the time stamp data are indicative of time stamps, and each of the time stamps is a number of cycles of the video clock in a predetermined audio period.

31. The transmitter of claim 30, wherein the predetermined audio period is P=X/(Y*Fs), where X and Y are integers.

32. The transmitter of claim 26, wherein the circuitry is configured to receive a stream of the embedded-clock auxiliary data, a code occurs periodically in the stream, and the sample clock changes state in response to each occurrence of the code in said stream.

33. The transmitter of claim 26, wherein the circuitry is configured to receive a stream of the embedded-clock auxiliary data, a code occurs periodically in the stream, and the sample clock changes state in response to each Nth occurrence of the code in said stream, where N is an integer.

34. The transmitter of claim 26, wherein the embedded-clock auxiliary data have a sample frequency, Fs, the sample clock signal has a frequency that is at least substantially equal to the sample frequency, Fs and the circuitry includes:

sample clock generation circuitry configured to generate the sample clock in response to the embedded-clock auxiliary data; and

time stamp data generation circuitry coupled to the sample clock generation circuitry and configured to use the sample clock signal as a periodic timing reference to generate the time stamp data.

35. The transmitter of claim 34, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

36. The transmitter of claim 34, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock and N and Y are integers.

37. The transmitter of claim 34, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate time stamp data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

38. The transmitter of claim 26, wherein the embedded-clock auxiliary data have a sample frequency, Fs, the sample clock signal has a frequency that is at least substantially equal to a predetermined fraction of the sample frequency, Fs, and the transmitter includes:

sample clock generation circuitry configured to generate the sample clock in response to the embedded-clock auxiliary data; and

time stamp data generation circuitry coupled to the sample clock generation circuitry and configured to use the sample clock signal as a periodic timing reference to generate the time stamp data.

39. The transmitter of claim 38, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

40. The transmitter of claim 38, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock and N and Y are integers.

41. The transmitter of claim 38, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate time stamp data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

42. The transmitter of claim 26, wherein the embedded-clock auxiliary data are SPDIF audio data, and the sample clock changes state in response to occurrences of synchronization codes embedded in the SPDIF audio data.

43. The transmitter of claim 26, wherein the embedded-clock auxiliary data are SPDIF audio data having sample frequency, Fs, and the sample clock changes state in response to each occurrence of a B, M, or W preamble in the SPDIF audio data.

44. The transmitter of claim 43, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock, and to generate time stamp data indicative of (N*Fp)/(Y*Fs), where Y is an integer.

45. The transmitter of claim 43, wherein the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock, where N and Y are integers.

46. The transmitter of claim 43, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and the time stamp data generation circuitry is configured to count the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then to count the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs, and to generate data indicative of (N/Y−

W)*Z+W*(Fp/Fs).

47. The transmitter of claim 26, wherein the circuitry is configured to remove jitter from the sample clock, thereby generating a stabilized version of the sample clock, and to generate the time stamp data in response to the video clock and the stabilized version of the sample clock.

48. The transmitter of claim 26, wherein the circuitry is configured to generate a first sequence of cycle time stamp values having a first average value in response to the video clock and the sample clock, and to process the cycle time stamp values to generate the time stamp data, wherein the time stamp data are indicative of a second sequence of cycle time stamp values having an average value at least substantially equal to the first average value, and wherein there is less variation among the cycle time stamps in the second sequence than among the cycle time stamps in the first sequence.

49. A time stamp generation circuit for use in a transmitter, said circuit including:

sample clock generation circuitry coupled and configured to extract a sample clock from a stream of embedded-clock auxiliary data without use of a phase-locked loop; and

time stamp data generation circuitry coupled to the sample clock generation circuitry and configured to generate time stamp data in response to a video clock and the sample clock, wherein the embedded-clock auxiliary data are indicative of samples of non-video auxiliary data that occur with a sample frequency, Fs, the time stamp data are indicative of time stamps, and each of the time stamps is a number of cycles of the video clock in a predetermined audio period.

50. The circuit of claim 49, wherein the predetermined audio period is P=X/(Y*Fs), where X and Y are integers.

51. The circuit of claim 49, wherein a code occurs periodically in the stream of embedded-clock auxiliary data, and the sample clock changes state in response to each occurrence of the code in said stream.

52. The circuit of claim 49, wherein a code occurs periodically in the stream of embedded-clock auxiliary data, and the sample clock changes state in response to each Nth occurrence of the code in said stream, where N is an integer.

53. The circuit of claim 49, wherein the embedded-clock auxiliary data are SPDIF audio data, and the sample clock changes state in response to occurrences of synchronization codes embedded in the SPDIF audio data.

54. The circuit of claim 49, wherein the embedded-clock auxiliary data are SPDIF audio data, and the sample clock changes state in response to each occurrence of a B, M, or W preamble in the SPDIF audio data.

55. A method for generating time stamp data, including the steps of:

(a) without use of a phase-locked loop, generating a sample clock in response to a stream of embedded-clock auxiliary data indicative of samples of non-video auxiliary data that occur with a sample frequency, Fs; and

(b) generating the time stamp data in response to a video clock and the sample clock, such that the time stamp data are indicative of time stamps and each of the time stamps is a number of cycles of the video clock in a predetermined auxiliary data period.

56. The method of claim 55, wherein the embedded-clock auxiliary data are embedded-clock audio data, the predetermined auxiliary data period is a predetermined audio period, and the predetermined audio period is P=X/(Y*Fs), where X and Y are integers.

57. The method of claim 55, wherein a code occurs periodically in the stream of embedded-clock auxiliary data, and step (a) includes the step of generating the sample clock such that said sample clock changes state in response to each occurrence of the code in said stream.

58. The method of claim 55, wherein a code occurs periodically in the stream of embedded-clock auxiliary data, and step (a) includes the step of generating the sample clock such that said sample clock changes state in response to each Nth occurrence of the code in said stream, where N is an integer.

59. The method of claim 55, wherein the embedded-clock auxiliary data are SPDIF audio data, and step (a) includes the step of generating the sample clock such that said sample clock changes state in response to occurrences of synchronization codes embedded in the SPDIF audio data.

60. The method of claim 55, wherein the embedded-clock auxiliary data are SPDIF audio data, and step (a) includes the step of generating the sample clock such that said sample clock changes state in response to each occurrence of a B, M, or W preamble in the SPDIF audio data.

61. The method of claim 55, wherein step (b) includes the steps of:

counting the number of cycles of the video clock that occur during N cycles of the sample clock, thereby determining N*(Fp/Fs), where Fp is the frequency of the video clock; and

generating the time stamp data such that said time stamp data are indicative of (N*Fp)/(Y*Fs), where Y is an integer.

62. The method of claim 55, wherein step (b) includes the step of:

counting the number of cycles of the video clock that occur during N/Y cycles of the sample clock, thereby determining (N*Fp)/(Y*Fs), where Fp is the frequency of the video clock, where N and Y are integers.

63. The method of claim 55, wherein Fp is the frequency of the video clock, N and Y are integers but N/Y is not a whole number, and step (b) includes the steps of:

counting the number of cycles of the video clock that occur during W cycles of the sample clock, where W is the whole number portion of N/Y, thereby determining W*(Fp/Fs), and then counting the number of cycles of the video clock that occur during the next cycle of the sample clock, thereby determining Z=Fp/Fs; and

generating the time stamp data such that said time stamp data are indicative of (N/Y−

W)*Z+W*(Fp/Fs).