Method for patterning a mask layer and semiconductor product

• US 20040081898A1
• Filed: 09/02/2003
• Published: 04/29/2004
• Est. Priority Date: 08/30/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Schilz, Christof Matthias, Kamm, Frank-Michael
• Granted Patent: US 7,078,135 B2
• Time in Patent Office: Days
• US Class Current: 430/5
• CPC Class Codes: G03F 1/62 Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
• CPC Class Codes: G03F 1/64 characterised by the frames, e.g. structure or material, including bonding means therefor

Abstract

During the lithographic exposure of layers to be patterned on semiconductor products, use is made of masks whose mask pattern is imaged on a reduced scale, with the aid of an imaging optical arrangement, onto the layer to be patterned. After the patterning of the mask layer, a membrane is placed onto the mask with a membrane holder in order to keep dust or other contaminants in the air away from the plane of the mask layer during the exposure. When the mask and the membrane holder are mounted, manufacturing-dictated height deviations thereof lead to subsequent distortion of the mask structure of the mask layer, which is transferred to the semiconductor product by means of the lithography. Here, the height tolerances of the mask and of the membrane holder are measured and a corrected mask pattern is calculated, the mask structures of which are offset in the lateral direction such that the mask distortions resulting from the mounting of the membrane holder are compensated for. The deformations of the mask and of the membrane holder perpendicular to the mask plane are compensated for by lateral displacements of the mask structures of the corrected mask pattern.

Claims

1. A method for patterning a mask layer of a mask, which comprises:

providing a mask with a mask layer, a membrane holder for mounting on the mask, and a membrane for protecting the mask layer from contaminants during a patterning of a layer with the mask;

prescribing an ideal mask pattern;

measuring height tolerances of the mask and the membrane holder in regions of contact therebetween in a mounted state;

calculating lateral distortions of the ideal mask pattern arising during a mounting of the membrane holder on the mask on account of the height tolerances;

transferring a corrected mask pattern onto the mask layer, the corrected mask pattern having compensation corrections relative to the ideal mask pattern, the compensation corrections compensating for the lateral distortions arising during the mounting of the membrane holder on the mask on account of the height tolerances; and

patterning the mask layer with the corrected mask pattern.

2. The method according to claim 1, which comprises measuring the height tolerances on a respective side of the mask and of the membrane holder in a vicinity of an edge thereof.

3. The method according to claim 1, which comprises measuring the height tolerances at corner regions of the mask and of the membrane holder.

4. The method according to claim 1, which comprises measuring the height tolerances in a region of edge centers of the mask and of the membrane holder.

5. The method according to claim 1, which comprises calculating the compensation corrections of the corrected mask pattern in dependence on a magnitude of a contact pressure with which the membrane holder is mounted on the mask.

6. The method according to claim 1, which comprises providing a torsionally rigid membrane made of an inorganic material as the membrane.

7. The method according to claim 6, which comprises calculating the compensation corrections of the corrected mask pattern in dependence on elastic properties of the inorganic material of the membrane.

8. The method according to claim 1, which comprises defining the compensation corrections as lateral displacements within a plane of the mask layer by which edges of structures of the ideal mask pattern are displaced.

9. The method according to claim 1, wherein the compensation corrections of the corrected mask pattern are non-rotationally symmetrical distortion corrections.

10. The method according to claim 1, which comprises transferring the corrected mask pattern to the mask layer with an electron beam writer.

11. The method according to claim 1, wherein the mask layer is a chromium layer.

12. The method according to claim 1, which comprises mounting the membrane holder with the membrane on the mask, and lithographically patterning a layer of a semiconductor substrate with the mask thus prepared.

13. The method according to claim 1, which comprises, subsequently to the patterning step, lithographically exposing a layer of a semiconductor product through the mask with the corrected mask pattern.

14. In a semiconductor product manufacturing process, a method of patterning a layer of the semiconductor product, which comprises:

patterning a mask with the method according to claim 1;

and

exposing and patterning the layer of the semiconductor product through the mask having the corrected mask pattern.

15. A semiconductor product having a patterned layer produced with a mask according to the method of claim 1.