Chip with molded cap array

• US 20040082104A1
• Filed: 12/08/2003
• Published: 04/29/2004
• Est. Priority Date: 01/10/2001
• Status: Active Grant

• Current Assignee: Nytell Software LLC (Intellectual Ventures LLC)
• Original Assignee: Silverbrook Research Pty Limited
• Inventors: Silverbrook, Kia
• Granted Patent: US 6,979,599 B2
• Time in Patent Office: Days
• US Class Current: 438/106
• CPC Class Codes: B29C 2035/0822 using IR radiation
• CPC Class Codes: B29C 2043/503 using ejector pins, rods
• CPC Class Codes: B29C 33/0022 Multi-cavity moulds B29C33/301 takes precedence
• CPC Class Codes: B29C 33/3842 Manufacturing moulds, e.g. shaping the mould surface by machining
• CPC Class Codes: B29C 43/36 Moulds for making articles of definite length, i.e. discrete articles
• CPC Class Codes: B81C 1/00333 Aspects relating to packaging of MEMS devices, not covered by groups B81C1/00269 - B81C1/00325
• CPC Class Codes: B81C 2203/0109 Bonding an individual cap on the substrate
• CPC Class Codes: B81C 2203/0127 Using a carrier for applying a plurality of packaging lids to the system wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1461 MEMS
• CPC Class Codes: Y10S 257/924 with passive device, e.g. capacitor, or battery, as integral part of housing or housing element, e.g. cap

Abstract

A chip is made by a method. The method provides an array of caps for protecting features on a semiconductor wafer. The array is fabricated by a novel method in which a two part mold is used. The array is made from a layer of thermoplastic material which is placed in the mold. Each cap in the array has a central portion and a perimeter wall. The mold is opened so that the array is carried by the first half. The array is applied to a wafer using the first half. After the arrays are applied, the wafer is separated into individual chips.

Claims

1. An individual chip with one or more protective polymeric wafer scale caps, made by a method, the method including:

a) forming, in a two part mold, an array of first hollow molded caps, from a layer of thermoplastic material which is placed in a mold, the mold having first and second mold halves which are brought together to form the caps, each cap having a central portion and a perimeter wall;

b) opening the mold so that the caps are carried by the first half;

c) applying, using the first half, the first caps to one side of a wafer;

then

d) separating the wafer into individual chips.

2. The chip made by the method of claim 1 wherein, the mold and the wafer are made from the same material.

3. The chip made by the method of claim 1 wherein, the mold is made from a semiconductor.

4. The chip made by the method of claim 1 wherein, the wafer is separated into individual packages by a etching of the wafer for which the first caps are a mask.

5. The chip made by the method of claim 1 wherein, applying the caps further comprises using a cooperating release wafer having eject pins to urge a cap into position.

6. The chip made by the method of claim 5 wherein, the first mold half has openings for receiving the pins, the pins being longer than the openings.

7. The chip made by the method of claim 5 wherein, there is a gap between the first mold half and the release wafer and using the release wafer further comprises applying a vacuum to the gap to draw the release wafer toward the first mold half.

8. The chip made by the method of claim 1 wherein, the cap is formed from a layer of thermoplastic material.

9. The chip made by the method of claim 8 wherein, forming the cap comprises heating the thermoplastic material with infrared radiation, the mold being essentially transparent to the infrared radiation.

10. The chip made by the method of claim 1 wherein, the first and second mold halves each have interior surfaces penetrated by holes for receiving pins which are formed on adjacent release wafers, the pins being longer than the holes but being flush with the interior surfaces during the forming.

11. The chip made by the method of claim 1 wherein, the thermoplastic material is 200-500 microns thick prior to being formed into caps.

12. The chip made by the method of claim 1 wherein, when the mold is closed, there is a thin layer of the material from which the caps are formed joining the caps into an array and the thin layer is removed by a squeezing action of the mold.

13. The chip made by the method of claim 1 wherein, when the mold is opened, there is a thin layer of the material from which the caps are formed joining the caps into an array and the thin layer is removed by an etching process.

14. The chip made by the method of claim 13 wherein, the thin layer is removed by an oxygen plasma etching.

15. The chip made by the method of claim 12, wherein, the first half has first portions which separate adjacent areas;

the second half has second portions which separate adjacent grooves;

the first and second portions coming together when the halves are brought together such that material is squeezed out from between the first and second portions, separating adjacent caps.

16. The chip made by the method of claim 1, wherein, the first mold half has a lower surface into which is formed a series of recesses defined by lateral edges, the second mold half having an upper surface in which is formed a series of grooves, the grooves aligning with the edges, the recesses and grooves defining cavities having a repeat spacing that corresponds to a spacing on a wafer to which the caps will be applied.

17. The chip made by the method of claim 15, wherein the first and second portions of the molds have not been etched.

18. The chip made by the method of claim 1, wherein:

the first half includes first holes formed through it;

there being provided a first half release wafer from which project pins;

the pins located in registry with the first holes;

the first half having a thickness in the area of the first holes, the pins being longer than the thickness;

the first half release wafer having a first position in which the pins are flush with interior ends of the first holes;

there being a gap between the first half and the first half release wafer when the first half release wafer is in the first position; and

wherein

a vacuum is applied to the gap to eject the caps.

19. The chip made by the method of claim 18, wherein:

the second half includes second holes formed through it;

there being provided a second half release wafer from which project pins;

the pins located in registry with the second holes;

the second half having a thickness in the area of the second holes, the pins being longer than the thickness;

the second half release wafer having a first position in which the pins are flush with an interior end of the second holes;

there being a second gap between the second half and the second half release wafer when the second half release wafer is in the first position.