Method for manufacturing a wafer level chip scale package

• US 20040082106A1
• Filed: 10/21/2003
• Published: 04/29/2004
• Est. Priority Date: 10/22/2002
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Dong-Ho, Jang, Dong-Hyeon, Lee, Jin-Hyuk, Kim, Gu-Sung
• Granted Patent: US 7,196,000 B2
• Time in Patent Office: Days
• US Class Current: 438/107
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/02145 Shape of the auxiliary member
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/05557 comprising protrusions or indentations
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]

Abstract

A semiconductor wafer with semiconductor chips having chip pads and a passivation layer is provided. First and second dielectric layers are sequentially formed on the passivation layer. The first and second dielectric layers form a ball pad area that includes an embossed portion, i.e., having a non-planar surface. A metal wiring layer is formed on the resulting structure including the embossed portion. A third dielectric layer is formed on the metal wiring layer. A portion of the third dielectric layer located on the embossed portion is removed to form a ball pad. A solder ball is formed on the embossed ball pad. With the embossed ball pad, the contact area between the solder balls and the metal wiring layer is increased, thereby improving the connection reliability.

Claims

1. A method for a wafer level chip scale package (CSP), the method comprising:

providing a semiconductor wafer, the semiconductor wafer including semiconductor chips having chip pads and a passivation layer, the wafer further including scribe lines between the chips;

forming a first patterned dielectric layer on the passivation layer to expose the chip pads; and

forming a second patterned dielectric layer on the first patterned dielectric layer to expose the chip pads,

wherein the second patterned dielectric layer has an embossed portion where a ball pad is to be formed.

2. The method of claim 1, wherein the embossed portion has a concave portion and a convex portion, the concave portion exposing a portion of the first patterned dielectric layer, the convex portion being formed of the second patterned dielectric layer.

3. The method of claim 2, wherein the concave portion comprises a circle shape, and the convex portion comprises a ring shape and having a smaller diameter than the concave portion.

4. The method of claim 2, wherein the convex portion comprises a discontinuous ring shape.

5. The method of claim 2, wherein the area of the concave portion inside the convex portion is approximately equal to the area of the convex portion.

6. The method of claim 1, further comprising:

forming a metal wiring layer on the first and second patterned dielectric layers including the embossed portion, the metal wiring layer being electrically connected to the chip pads;

forming a third dielectric layer on the metal wiring layer; and

removing a portion of the third dielectric layer over the embossed portion to form a connection hole therein, the connection hole exposing a portion of the metal wiring layer to form the ball pad.

7. The method of claim 6, further comprising:

forming a solder ball on the ball pad; and

cutting the semiconductor wafer along the scribe lines.

8. The method of claim 3, wherein forming a first patterned dielectric layer comprises exposing a portion of the passivation layer inside the ring-shaped second dielectric layer.

9. The method of claim 8, wherein forming a second patterned dielectric layer comprises exposing a portion of the passivation layer inside the ring-shaped second dielectric layer.

10. A method for a wafer level chip scale package (CSP) comprising:

providing a semiconductor wafer, the semiconductor wafer including semiconductor chips each having chip pads and a passivation layer;

forming a first dielectric layer on the passivation layer;

patterning the first dielectric layer to expose the chip pads;

forming a second dielectric layer on the patterned first dielectric layer; and

patterning the second dielectric layer to expose the chip pads,

wherein the first and second patterned dielectric layers form a ball pad area, in which the second patterned dielectric layer has a non-planar surface.

11. The method of claim 10, further comprising:

forming a metal wiring layer on the first and second patterned dielectric layers, the metal wiring layer being electrically connected to the chip pads;

forming a third dielectric layer on the metal wiring layer; and

removing a portion of the third dielectric layer over the non-planar surface to form a connection hole therein, the connection hole exposing a portion of the metal wiring layer over the non-planar surface to form a ball pad.

12. The method of claim 11, further comprising:

forming a solder ball on the ball pad.

13. A wafer level chip scale package (CSP), comprising:

a semiconductor chip having chip pads and a passivation layer exposing chip pads;

a first patterned dielectric layer disposed on the passivation layer; and

a second patterned dielectric layer, the first and second patterned dielectric layers exposing the chip pads,

wherein the first and second patterned dielectric layers have an embossed portion comprising a concave portion and a convex portion, the concave portion exposing a portion of the first patterned dielectric layer where a ball pad is to be formed, the convex portion being formed of the second patterned dielectric layer.

14. The apparatus of claim 13, wherein the concave portion comprises a circle shape, and the convex portion comprises a ring shape and having a smaller diameter than the concave portion.

15. The apparatus of claim 13, wherein the convex portion comprises a discontinuous ring shape.

16. The apparatus of claim 13, wherein the area of the concave portion inside the convex portion is approximately equal to the area of the convex portion.

17. The method of making the wafer level chip scale package (CSP) of claim 13, the method comprising:

providing a semiconductor wafer, the semiconductor wafer including a semiconductor chip having chip pads and a passivation layer, the wafer further including scribe lines between the chips;

forming a first patterned dielectric layer on the passivation layer to expose the chip pads; and

forming a second patterned dielectric layer on the first patterned dielectric layer to expose the chip pads, wherein the second patterned dielectric layer has an embossed portion where a ball pad is to be formed.