Method of fabricating a high-voltage transistor with a multi-layered extended drain structure
First Claim
1. A method for fabricating an extended drain region of a high-voltage transistor comprising:
- forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;
etching the epitaxial layer to form a pair of spaced-apart trenches that define a mesa with first and second sidewall portions;
forming a dielectric layer in each of the trenches, the dielectric layer partially filling each of the trenches and covering the first and second sidewall portions;
filling a remaining portion of the trenches with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer.
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Abstract
A method for fabricating a high-voltage transistor with an extended drain region comprises forming an epitaxial layer on a substrate, the epitaxial layer and the substrate being of a first conductivity type; then etching the epitaxial layer to form a pair of spaced-apart trenches that define first and second sidewall portions of the epitaxial layer. A dielectric layer is formed that partially fills each of the trenches, covering the first and second sidewall portions. The remaining portions of the trenches are then filled with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer.
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Citations
33 Claims
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1. A method for fabricating an extended drain region of a high-voltage transistor comprising:
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forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;
etching the epitaxial layer to form a pair of spaced-apart trenches that define a mesa with first and second sidewall portions;
forming a dielectric layer in each of the trenches, the dielectric layer partially filling each of the trenches and covering the first and second sidewall portions;
filling a remaining portion of the trenches with a conductive material to form first and second field plate members that are insulated from the substrate and the epitaxial layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for fabricating a high-voltage transistor comprising:
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forming an epitaxial layer on a substrate, the epitaxial layer being of a first conductivity type and having a top surface;
forming source and body regions in the epitaxial layer, the source region being of the first conductivity type and disposed at the top surface of the epitaxial layer, the body region being of a second conductivity type opposite to the first conductivity type;
forming a pair of spaced-apart trenches in the epitaxial layer that define a mesa with first and second sidewall portions;
forming a dielectric layer in each of the trenches that covers the first and second sidewall portions;
forming field plate members in the trenches, the field plate members comprising a conductive material that is insulated from the mesa; and
forming an insulated gate member between each of the field plate members and the mesa, a channel being defined adjacent the insulated gate member in the mesa across the body region. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A method of fabricating a high-voltage transistor on a substrate, the method comprising:
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forming a plurality of parallel arranged drift regions oriented in a first direction, each of the drift regions comprising a doped semiconductor layer of a first conductivity type interleaved with an insulating layer and a conducting layer, the conducting layer being insulated from the doped semiconductor layer by the insulating layer, the conducting layer comprising a field plate member of the high-voltage transistor;
forming source and body regions, the source region being of the first conductivity type and the body region being of a second conductivity type opposite to the first conductivity type, the body region separating the source region from the drift regions; and
forming an insulated gate adjacent the body region, the insulated gate defining a channel in the body region between the source region and the drift regions. - View Dependent Claims (26, 27, 28, 29, 30, 31, 32, 33)
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Specification