Structure and method for forming self-aligned bipolar junction transistor with expitaxy base
First Claim
1. A method for forming a self-aligned Bipolar Junction Transistor with expitaxy base comprising:
- forming a oxide layer on a semiconductor substrate;
forming a first polysilicon layer over said oxide layer, said first polysilicon layer with first type ion;
removing said first polysilicon layer partly to expose said oxide layer, thereby forming a emitter window;
performing a second type ion implantation to form a collector region in said substrate and below said emitter window, wherein said second type ion'"'"'s is opposite to said first type ion'"'"'s conductive type;
removing said oxide layer inside said emitter window;
forming a expitaxy base layer over said first polysilicon layer and said semiconductor substrate to form a base region on said collector region, wherein said expitaxy base has said first type ion;
forming a dielectric layer over said expitaxy base;
etching said dielectric layer to form a inner spacer on sidewalls of said expitaxy base inside said emitter window;
forming a second polysilicon layer over said expitaxy base and said emitter window, wherein said second polysilicon layer has second type ion;
and etching said second polysilicon layer to form emitter plug, that is self-aligned to said emitter window.
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Abstract
The present invention proposes a novel method to fabricate a Bipolar Junction Transistor device. The steps of the present invention include forming a shallow trench isolation structure in a substrate. An oxide layer is formed on the substrate. Subsequently, a polysilicon layer is next formed on the oxide layer, and the polysilicon layer has first type ion. Successively, a polysilicon layer is patterned on the oxide layer. The next step is to perform a second type ion implantation, thereby forming a collector region in the substrate and below the emitter window. The oxide layer is removed inside the emitter window. An expitaxy base is then formed on the polysilicon layer and substrate, thereby forming base region on the collector region, wherein the expitaxy base has the first type ion. After the expitaxy base is formed, a dielectric layer is formed over the expitaxy base. Next, the dielectric layer is etched to form inner spacer on sidewalls of the expitaxy base inside the emitter window. A second polysilicon layer is formed over the expitaxy base and the emitter window, wherein the second polysilicon layer has the second type ion. Finally, an etching process is introduced to etch the second polysilicon layer to form emitter plug. That is self-aligned to the emitter window.
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Citations
36 Claims
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1. A method for forming a self-aligned Bipolar Junction Transistor with expitaxy base comprising:
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forming a oxide layer on a semiconductor substrate;
forming a first polysilicon layer over said oxide layer, said first polysilicon layer with first type ion;
removing said first polysilicon layer partly to expose said oxide layer, thereby forming a emitter window;
performing a second type ion implantation to form a collector region in said substrate and below said emitter window, wherein said second type ion'"'"'s is opposite to said first type ion'"'"'s conductive type;
removing said oxide layer inside said emitter window;
forming a expitaxy base layer over said first polysilicon layer and said semiconductor substrate to form a base region on said collector region, wherein said expitaxy base has said first type ion;
forming a dielectric layer over said expitaxy base;
etching said dielectric layer to form a inner spacer on sidewalls of said expitaxy base inside said emitter window;
forming a second polysilicon layer over said expitaxy base and said emitter window, wherein said second polysilicon layer has second type ion;
andetching said second polysilicon layer to form emitter plug, that is self-aligned to said emitter window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 33, 34)
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21. A bipolar junction transistor with expitaxy base comprising:
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forming a oxide layer on a semiconductor substrate;
forming a polysilicon layer over said oxide layer, and removing said polysilicon layer partly to form a emitter window on said oxide layer, said polysilicon layer with first type ion;
forming a collector region in said substrate and below said emitter window, wherein said collector region has a second type ion'"'"'s, said second type ion'"'"'s is opposite to said first type ion'"'"'s conductive type;
forming a expitaxy base layer over said first polysilicon layer and said semiconductor substrate to form a base region on said collector region after removing said oxide layer inside said emitter window, wherein said expitaxy base has said first type ion;
forming a inner spacer on sidewalls of said expitaxy base inside said emitter window;
forming a emitter plug over said expitaxy base and said emitter window, wherein said emitter plug has second type ion;
removing parts of said expitaxy base layer and said ploysilicon layer to form poly base interconnect pattern; and
forming a patterned salicide layer on said expitaxy base, said emitter plug and over said expitaxy base, said ploysilicon layer. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 35, 36)
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Specification