Method of making metallization and contact structures in an integrated circuit using a timed trench etch
First Claim
1. A method for forming metallization and contact structures in an integrated circuit comprising:
- a) etching a trench dielectric layer of a composite structure comprising in sequential order;
i) a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to said gate structure;
ii) a contact dielectric layer; and
iii) a trench dielectric layer;
to form a trench in said trench dielectric layer under etch conditions which do not substantially etch said contact dielectric layer;
b) etching said contact dielectric layer under conditions which do not substantially etch said contact dielectric layer;
substantially damage said gate structure to form a first contact opening that exposes a region of said semiconductor substrate and a portion of at least one of said dielectric spacers; and
c) depositing a conductive material into said contact opening and said trench.
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Accused Products
Abstract
The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.
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Citations
18 Claims
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1. A method for forming metallization and contact structures in an integrated circuit comprising:
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a) etching a trench dielectric layer of a composite structure comprising in sequential order;
i) a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to said gate structure;
ii) a contact dielectric layer; and
iii) a trench dielectric layer;
to form a trench in said trench dielectric layer under etch conditions which do not substantially etch said contact dielectric layer;
b) etching said contact dielectric layer under conditions which do not substantially etch said contact dielectric layer;
substantially damage said gate structure to form a first contact opening that exposes a region of said semiconductor substrate and a portion of at least one of said dielectric spacers; and
c) depositing a conductive material into said contact opening and said trench. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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Specification