Integrated packet bit error rate tester for 10G SERDES
First Claim
1. An integrated packet bit error rate tester comprising:
- a packet transmit circuit including a first memory for storing transmit packet data and connectable to a channel under test;
a packet receive circuit including a second memory for storing received packet compare data and connectable to the channel under test; and
an interface for programming the packet transmit and packet receive circuits, wherein the packet transmit circuit can generate an arbitrary packet pattern in response to commands from the interface, and wherein the packet receive circuit can determine a bit error rate of the channel under test.
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Accused Products
Abstract
An integrated packet bit error rate tester includes a packet transmit circuit that has a first memory for storing transmit packet data and is connectable to a channel under test. A packet receive circuit includes a second memory for storing received packet data and is connectable to the channel under test. An interface is used for programming the packet transmit and packet receive circuits. The packet transmit circuit can generate an arbitrary 10G SERDES packet in response to commands from the interface. The packet receive circuit can determine a bit error rate of the channel under test. The second memory can capture received packet data upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, and (c) after an error is detected.
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Citations
53 Claims
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1. An integrated packet bit error rate tester comprising:
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a packet transmit circuit including a first memory for storing transmit packet data and connectable to a channel under test;
a packet receive circuit including a second memory for storing received packet compare data and connectable to the channel under test; and
an interface for programming the packet transmit and packet receive circuits, wherein the packet transmit circuit can generate an arbitrary packet pattern in response to commands from the interface, and wherein the packet receive circuit can determine a bit error rate of the channel under test. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. An integrated packet bit error rate tester comprising:
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a packet transmit circuit including a first memory for storing transmit packet data and connectable to a channel under test;
a packet receive circuit including a second memory for capturing received packet compare data from the channel under test; and
an interface for programming the packet transmit and packet receive circuits, wherein the packet transmit circuit can generate an arbitrary SERDES packet pattern in response to commands from the interface, and wherein the packet receive circuit can determine a bit error rate of the channel under test based on the transmit packet data compared to the receive packet data. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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38. An integrated packet bit error rate tester comprising:
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a packet transmit circuit including a first memory for storing transmit packet data and connectable to a channel under test; and
a packet receive circuit including a second memory for capturing received packet data from the channel under test upon any one of (a) after a pre-programmed pattern is detected, (b) after a pre-programmed pattern is lost, (c) after an error is detected, and (d) immediately. - View Dependent Claims (39, 40)
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41. A method of testing bit error rate of a channel comprising:
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generating a test packet including an arbitrary marker pattern;
transmitting the test packet over the channel;
capturing the test packet from the channel; and
determining the bit error rate of the channel based on the test packet. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53)
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Specification