Selector with group identification terminals

• US 20040083314A1
• Filed: 06/23/2003
• Published: 04/29/2004
• Est. Priority Date: 03/26/1999
• Status: Abandoned Application

• Current Assignee: Fourie Incorporated
• Original Assignee: Fourie Incorporated
• Inventors: Nishida, Shinsuke
• Application Number:
  US10/600,578
• Publication Number:
  US 20040083314A1
• Time in Patent Office: Days
• US Class Current: 710/3
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The selector receives group identification signals which specify any number of divisions for elements to be grouped and address signals that specify one of the divided groups. The groups are then obtained based on the number of divisions specified with the group identification signals. The selector further selects selector-output terminals within a group, of the groups, that is specified with the address signals. The effective selector-output signals are then output from the selected selector-output terminals.

Claims

1. A selector comprising:

a plurality of address terminals;

a plurality of selector-output terminals; and

a plurality of group identification terminals which receive group identification signals that contain information about number of divisions into which said selector-output terminals are to be divided into groups,

wherein, of the groups divided based on the number of divisions specified by the group identification signals, the group specified with the address signals is selected based on the group identification signals that are input from said group identification terminals and the address signals that are input from said address terminals, and the selector-output signal that is to be output from the selector-output terminal within the selected group is made effective.

2. The selector according to claim 1, wherein a particular selector-output terminal of said plurality of selector-output terminals is specified with addresses obtained by,

dividing said plurality of selector-output terminals into a plurality of groups in a first division unit,

assigning an address that identifies a corresponding group to each of the divided groups,

further dividing each of the groups divided in the first division unit into a plurality of groups in a second division unit,

assigning an address that identifies a corresponding group to each of the groups divided in the second division unit,

repeating division of groups and assignment of addresses to the divided groups for a specified number of times,

wherein the group identification signal is a signal that specifies the number of divisions, and

wherein the address signal is a signal that specifies one of the addresses that are assigned to the divided groups.

3. The selector according to claim 1, wherein a particular selector-output terminal of said plurality of selector-output terminals is specified with addresses obtained by,

dividing said plurality of selector-output terminals into groups each of which includes one quarter of the terminals,

assigning 2-bit addresses of “

00”

, “

01”

, “

10”

, and “

11”

to the divided groups,

further dividing each of the divided groups into groups each of which includes one quarter of the group,

further assigning 2-bit addresses of “

00”

, “

01”

, “

10”

, and “

11”

to each of the divided groups, and

repeating division of groups and assignment of addresses to the divided groups for a specified number of times,

wherein the group identification signal is a signal that specifies the number of divisions, and

wherein the address signal is a signal that specifies one of the addresses that are assigned to the divided groups.

4. A selector comprising:

a plurality of address terminals;

a plurality of selector-output terminals;

a plurality of group identification terminals which receive group identification signals that contain information about number of divisions into which said selector-output terminals are to be divided into groups; and

a selection output terminal which outputs a selection signal that identifies the selector-output signals that are output from said selector-output terminal,

wherein, of the groups divided based on the number of divisions specified by the group identification signals, the group specified with the address signals is selected based on the group identification signals that are input from said group identification terminals and the address signals that are input from said address terminals, and the selector-output signal that is to be output from the selector-output terminal within the selected group is made effective, and a selection signal that identifies the selector-output signals that are output in response to input of the address signals is output from said selection output terminal.

5. The selector according to claim 4, wherein a particular selector-output terminal of said plurality of selector-output terminals is specified with addresses obtained by,

dividing said plurality of selector-output terminals into a plurality of groups in a first division unit,

assigning an address that identifies a corresponding group to each of the divided groups,

further dividing each of the groups divided in the first division unit into a plurality of groups in a second division unit,

assigning an address that identifies a corresponding group to each of the groups divided in the second division unit,

repeating division of groups and assignment of addresses to the divided groups for a specified number of times,

wherein the group identification signal is a signal that specifies the number of divisions, and

wherein the address signal is a signal that specifies one of the addresses that are assigned to the divided groups.

6. The selector according to claim 4, wherein a particular selector-output terminal of said plurality of selector-output terminals is specified with addresses obtained by,

dividing said plurality of selector-output terminals into groups each of which includes one quarter of the terminals,

assigning 2-bit addresses of “

00”

, “

01”

, “

10”

, and “

11”

to the divided groups,

further dividing each of the divided groups into groups each of which includes one quarter of the group,

further assigning 2-bit addresses of “

00”

, “

01”

, “

10”

, and “

11”

to each of the divided groups, and

repeating division of groups and assignment of addresses to the divided groups for a specified number of times,

wherein the group identification signal is a signal that specifies the number of divisions, and

wherein the address signal is a signal that specifies one of the addresses that are assigned to the divided groups.