Method and apparatus for managing the integrity of data in non-volatile memory system

• US 20040083334A1
• Filed: 10/02/2003
• Published: 04/29/2004
• Est. Priority Date: 10/28/2002
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Qawami, Bahman, Sabet-Sharghi, Farshid, Chang, Robert C.
• Application Number:
  US10/679,000
• Publication Number:
  US 20040083334A1
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 2211/109 Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation

Abstract

Methods and apparatus for encoding data associated with a page by dividing the page into segments and separately encoding the segments using extended error correction code (ECC) calculations are disclosed. According to one aspect of the present invention, a method for encoding data associated with a page which has a data area and an overhead area within a non-volatile memory of a memory system includes dividing at least a part of the page into at least two segments of the data, the at least two segments of the data including a first segment and a second segment, and performing ECC calculations on the first segment to encode the first segment. The method also includes performing the ECC calculations on the second segment to encode the second segment substantially separately from the first segment.

Claims

1. A method for encoding data associated with a page within a non-volatile memory of a memory system, the page having a data area and an overhead area, the method comprising:

dividing at least a part of the page into at least two segments of the data, the at least two segments of the data including a first segment and a second segment;

performing error correction code (ECC) calculations on the first segment to encode the first segment; and

performing the ECC calculations on the second segment to encode the second segment, wherein the second segment is encoded substantially separately from the first segment.

2. The method of claim 1 wherein the first segment includes the data area and the second segment includes the overhead area.

3. The method of claim 1 wherein the first segment includes a first section of the data area and the second segment includes a second section of the data area.

4. The method of claim 1 wherein the ECC calculations are associated with an ECC algorithm that is arranged to detect up to two incorrect bits and to correct up to one of the incorrect bits in each of the first segment and the second segment.

5. The method of claim 4 wherein the ECC algorithm is a Hamming Code ECC algorithm.

6. The method of claim 1 wherein dividing the at least part of the page into the at least two segments of the data includes:

dividing the page into three segments, the three segments including the first segment, the second segment, and a third segment.

7. The method of claim 6 further including:

performing the ECC calculations on the third segment to encode the third segment, wherein the third segment is encoded substantially separately from the first segment and the second segment.

8. The method of claim 6 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes the overhead area.

9. The method of claim 6 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes a third section of the data area.

10. The method of claim 1 wherein the non-volatile memory is one of a NAND flash memory and an MLC NAND flash memory.

15. The memory system of claim 1 wherein the ECC calculations are associated with an ECC algorithm that is arranged to detect up to two incorrect bits and to correct up to one of the incorrect bits in each of the first segment and the second segment.

16. The memory system of claim 15 wherein the ECC algorithm is a Hamming Code ECC algorithm.

26. The memory system of claim 1 wherein the ECC calculations are associated with a Hamming Code ECC algorithm that is arranged to correct up to one incorrect bit included in the first segment and up to one incorrect bit included in the second segment.

11. A memory system comprising:

a non-volatile memory, the non-volatile memory including a page, the page having a data area and an overhead area, the data area and the overhead area being arranged to contain bits of data;

code devices for dividing at least a part of the page into at least two segments, the at least two segments including a first segment and a second segment;

code devices for performing error correction code (ECC) calculations on the first segment to encode the first segment and on the second segment to encode the second segment, wherein the second segment is encoded substantially separately from the first segment; and

a memory area for storing the code devices.

12. The memory system of claim 11 further including:

a controller, the controller being arranged to process the code devices.

13. The memory system of claim 11 wherein the first segment includes the data area and the second segment includes the overhead area.

14. The memory system of claim 11 wherein the first segment includes a first section of the data area and the second segment includes a second section of the data area.

17. The memory system of claim 11 wherein the code devices for dividing the at least part of the page into the at least two segments include:

code devices for dividing the page into three segments, the three segments including the first segment, the second segment, and a third segment.

18. The memory system of claim 17 further including:

code devices for performing the ECC calculations on the third segment to encode the third segment, wherein the third segment is encoded substantially separately from the first segment and the second segment.

19. The memory system of claim 17 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes the overhead area.

20. The memory system of claim 17 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes a third section of the data area.

21. The memory system of claim 11 wherein the non-volatile memory is one of a NAND flash memory and an MLC NAND flash memory.

22. The memory system of claim 11 wherein the code devices are one of software code devices and firmware code devices.

23. A memory system comprising:

a non-volatile memory, the non-volatile memory including a page, the page having a data area and an overhead area, the data area and the overhead area being arranged to contain bits of data;

means that divide at least a part of the page into at least two segments, the at least two segments including a first segment and a second segment; and

means that perform error correction code (ECC) calculations on the first segment to encode the first segment and on the second segment to encode the second segment, wherein the second segment is encoded substantially separately from the first segment.

24. The memory system of claim 23 wherein the first segment includes the data area and the second segment includes the overhead area.

25. The memory system of claim 23 wherein the first segment includes a first section of the data area and the second segment includes a second section of the data area.

27. The memory system of claim 23 wherein the means that divide the at least part of the page into the at least two segments include:

means that divide the page into three segments, the three segments including the first segment, the second segment, and a third segment.

28. The memory system of claim 27 further including:

means that perform the ECC calculations on the third segment to encode the third segment, wherein the third segment is encoded substantially separately from the first segment and the second segment.

29. The memory system of claim 27 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes the overhead area.

30. The memory system of claim 27 wherein the first segment includes a first section of the data area, the second segment includes a second section of the data area, and the third segment includes a third section of the data area.

31. The memory system of claim 23 wherein the non-volatile memory is one of a NAND flash memory and an MLC NAND flash memory.