Copper interconnect by immersion/electroless plating in dual damascene process

• US 20040084320A1
• Filed: 10/30/2002
• Published: 05/06/2004
• Est. Priority Date: 10/30/2002
• Status: Abandoned Application

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Wong, Kaiser H.
• Application Number:
  US10/284,557
• Publication Number:
  US 20040084320A1
• Time in Patent Office: Days
• US Class Current: 205/123
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition

Abstract

A method of fabrication of copper interconnect by means of copper electroplating is disclosed. In the conventional method of fabricating copper interconnect for integrated circuits, critical steps such as deposition of copper seed layer and chemical mechanical polishing (CMP) are required. However in this invention, both the seed layer deposition and CMP are not required.

Claims

1. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:

providing silicon wafer as an active surface having a bottom metal layer;

depositing a diffusion layers patterned to define areas having trenches and vias;

connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and

and copper electroplating said silicon wafer.

2. The copper electroplating method according to claim 1, further comprising:

said silicon wafer is a n-type silicon wafer.

3. The copper electroplating method according to claim 1, further comprising:

depositing tantalum patterned to the defined areas in the trenches and vias.

4. The copper electroplating method according to claim 1, further comprising:

depositing field oxide, nitride, and oxide layers with a barrier layer of tantalum to form the trenches and vias

5. The copper electroplating method according to claim 4, further comprising:

depositing within the nitride layer a gate oxide having deposited thereon a gate electrode.

6. The copper electroplating method according to claim 1, further comprising:

providing a PMOS structure for electroplating.

7. The copper electroplating method according to claim 1, further comprising:

providing a CMOS structure for electroplating with a bias power supply connected between a P−

well layer and a n-type substrate.

8. The copper electroplating method according to claim 1, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply.

9. The copper electroplating method according to claim 1, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply and twin well layers consisting of N−

epitaxy and N+ substrate are connected to a cathode.

10. The copper electroplating method according to claim 1, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply with a bias power supply connected between a P−

well layer and a n-type substrate.

11. The copper electroplating method according to claim 1, further comprising:

providing a diode device having a n-type substrate connected to an anode for copper eletroplating.

12. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:

providing transistor structure defining an active surface having a bottom metal layer;

depositing a diffusion layers patterned to define areas having trenches and vias and forming a source, drain, gate electrodes;

connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and

and copper electroplating said transistor structure.

13. The copper electroplating method according to claim 12, further comprising:

depositing within the nitride layer a gate oxide having deposited thereon a gate electrode.

14. The copper electroplating method according to claim 12, further comprising:

providing a PMOS structure for electroplating.

15. The copper electroplating method according to claim 12, further comprising:

providing a CMOS structure for electroplating with a bias power supply connected between a P−

well layer and a n-type substrate.

16. The copper electroplating method according to claim 12, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply.

17. The copper electroplating method according to claim 12, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply and twin well layers consisting of N−

epitaxy and N+ substrate are connected to a cathode.

18. The copper electroplating method according to claim 12, further comprising:

providing a CMOS structure for electroplating wherein a P−

well layer is connected to an anode of a power supply with a bias power supply connected between a P−

well layer and a n-type substrate.

19. The copper electroplating method according to claim 12, further comprising:

providing a diode structure having a n-type substrate connected to an anode for copper eletroplating.

20. A copper electroplating method for fabrication of copper interconnect for integrated circuits, comprising:

providing transistor structure defining an active surface having a bottom metal layer;

depositing a diffusion layers patterned to define areas having trenches and vias and forming a source, drain, gate electrodes;

depositing field oxide, nitride, and oxide layers with a barrier layer of tantalum to form the trenches and vias

depositing tantalum patterned to the defined areas in the trenches and vias;

connecting a negative terminal of a power supply to contact to the bottom metal layer of the wafer; and

and copper electroplating said transistor structure.