Stacked organic memory devices and methods of operating and fabricating

• US 20040084670A1
• Filed: 11/04/2002
• Published: 05/06/2004
• Est. Priority Date: 11/04/2002
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Okoroanyanwu, Uzodinma, Tripsas, Nicholas H., Pangrle, Suzette K., VanBuskirk, Michael A.
• Granted Patent: US 6,870,183 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 11/5664 using organic memory material storage elements
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: H10K 19/00 Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
• CPC Class Codes: H10K 85/111 comprising aromatic, heteroaromatic, or aryl chains, e.g. polyaniline, polyphenylene or polyphenylene vinylene
• CPC Class Codes: H10K 85/113 Heteroaromatic compounds comprising sulfur or selene, e.g. polythiophene
• CPC Class Codes: H10K 85/114 Poly-phenylenevinylene; Derivatives thereof
• CPC Class Codes: H10K 85/143 Polyacetylene; Derivatives thereof
• CPC Class Codes: H10K 85/30 Coordination compounds
• CPC Class Codes: H10K 85/311 Phthalocyanine

Abstract

The present invention provides a multi-layer organic memory device that can operate as a non-volatile memory device having a plurality of stacked and/or parallel memory structures constructed therein. A multi-cell and multi-layer organic memory component can be formed with two or more electrodes having a selectively conductive media between the electrodes forming individual cells, while utilizing a partitioning component to enable stacking of additional memory cells on top of or in association with previously formed cells. Memory stacks can be formed by adding additional layers—respective layers separated by additional partitioning components, wherein multiple stacks can be formed in parallel to provide a high-density memory device.

Claims

1. An organic memory device, comprising:

at least a first organic memory structure and a second organic memory structure arranged in a vertical manner with respect to each other; and

at least one control component to partition the first and second organic memory structures, the at least one control component facilitates access to at least one of the first organic memory structure and the second organic memory structure.

2. The memory device of claim 1, further comprising one or more vertical columns having at least two organic memory structures per column.

3. The memory device of claim 2, the one or more vertical columns are formed in accordance with a damascene/via process.

4. The memory device of claim 2, the one or more vertical columns are formed in accordance with a stacked pillar process.

5. The memory device of claim 1, the control component further comprises at least one of a diode, a thin-filmed diode (TFD), a zener diode, an LED, a transistor, a thin-filmed transistor (TFT), a Silicon Controlled Rectifier (SCR), Uni Junction Transistor (UJT), and a Field Effect Transistor (FET).

6. The memory device of claim 3, the TFD is an organic device having a polymer layer formed between a cathode electrode and an anode electrode.

7. The memory device of claim 1, the first and second organic memory structures further comprising:

a first electrode;

a selectively conductive media formed on the first electrode, the selectively conductive media comprising a passive layer formed on the first electrode and an organic layer formed on the passive layer; and

at least one other electrode formed on the organic layer and operative with the first electrode to activate a memory portion in the organic layer.

8. The memory device of claim 7, further comprising one or more global access lines to facilitate access to a plurality of organic memory structures.

9. The memory device of claim 7, the organic layer is an organic polymer layer formed on the passive layer.

10. The memory device of claim 9, the passive layer comprising a plurality of individual passive layers.

11. The memory device of claim 9, the passive layer contains Cu₂S.

12. The memory device of claim 9, the organic layer being a conjugated organic material.

13. The memory device of claim 9, the organic layer being selected from the group comprising:

polyacetylene, polyphenylacetylene, polydiphenylacetylene, polyaniline, poly(p-phenylene vinylene), polythiophene, polyporphyrins, porphyrinic macrocycles, thiol derivatized polyporphyrins, polymetallocenes, polyferrocenes, polyphthalocyanines, polyvinylenes, and polypyrroles.

14. The memory device of claim 9, at least one of the first electrode and the other electrode comprising a material being selected from the group comprising aluminum, chromium, copper, germanium, gold, magnesium, manganese, indium, iron, nickel, palladium, platinum, silver, titanium, zinc, alloys thereof, indium-tin oxide, polysilicon, doped amorphous silicon, and metal silicides.

15. The memory device of claim 14, further comprising a barrier layer to mitigate diffusion of the electrodes.

16. The memory device of claim 15, the barrier layer further comprising at least one of cobalt, chromium, nickel, palladium, tantalum, tantalum silicon nitride, titanium, titanium nitride, silicon nitride, tungsten nitride, and tungsten silicon nitride.

17. The memory device of claim 15, the at least one of the first electrode and the other electrode formed in accordance with at least one of a single damascene process and a dual damascene process.

18. The memory device of claim 1, further comprising a plurality memory cells, respective cells adapted in accordance with claim 2, the plurality of memory cells forming a non-volatile memory device.

19. The memory device of claim 18, further comprising one or more word lines to access the plurality of memory cells.

20. The memory device of claim 18, the non-volatile memory device employed as component in a computer system.

21. A method of fabricating an organic memory device, comprising:

forming a first electrode on a substrate;

forming a passive layer on the first electrode;

forming a dielectric layer over the passive layer;

forming a via in the dielectric layer;

filling the via with organic material;

forming at least one other electrode on the organic material; and

forming a switching device over the at least one other electrode to facilitate stacking of organic memory structures.

22. The method of claim 21, further comprising forming a plurality of organic memory structures, respective memory structures separated by a switching device.

23. The method of claim 22, further comprising forming the plurality of organic memory structures in at least one vertical column.

24. The method of claim 21, further comprising forming the first electrode and the at least one other electrode in accordance with at least one of a single damascene process and a dual damascene process.

25. The method of claim 24, further comprising forming a barrier layer to mitigate diffusion of the first electrode and the at least one other electrode into a subsequent layer.

26. The method of claim 21, further comprising forming at least one word line to access a plurality of memory cells fabricated in accordance with claim 21.

27. The method of claim 21, further comprising filling the via in accordance with a chemical vapor deposition process.

28. The method of claim 21, further comprising filling the via in accordance with a gas phase reaction process.

29. The method of claim 21, further comprising filling the via in accordance with a spin coating process.

30. A method of fabricating an organic memory device, comprising:

forming a first electrode on a substrate;

forming a passive layer on the first electrode;

forming an organic layer over the passive layer;

forming at least one other electrode on the organic layer; and

forming a switching device layer over the at least one other electrode to facilitate stacking of organic memory structures.

31. The method of claim 30, further comprising etching a plurality of organic memory stacks, respective memory stacks separated by the switching device layer.

32. The method of claim 31, further comprising forming the plurality of memory stacks in at least one vertical column.

33. A system for fabricating an organic memory device, comprising:

means for forming at least two organic memory structures arranged in a vertical manner with respect to each other; and

means for partitioning the at least two organic memory structures, the means for partitioning facilitates access to the organic memory structures.

34. An organic memory device, comprising:

a first memory structure comprising;

a first electrode;

a passive layer associated with the at least one bit line;

an organic semiconductor material formed over the passive layer; and

at second electrode formed over the organic semiconductor material to form a memory within the organic semiconductor material;

at least a second memory structure configured similarly to the first memory structure; and

at least one thin-filmed diode separating the first and second memory structures, the first memory structure and the second memory structure arranged in at least one column.

35. The organic memory device of claim 34, further comprising a plurality of multicell structures packaged as an Integrated Circuit.