Capacitive charge pump

• US 20040085104A1
• Filed: 10/30/2002
• Published: 05/06/2004
• Est. Priority Date: 10/30/2002
• Status: Active Grant

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Sanchez, Hector
• Granted Patent: US 6,844,762 B2
• Time in Patent Office: Days
• US Class Current: 327/157
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 4/023 by repetitive charge or discharge of a capacitor, analogue generators
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence
• CPC Class Codes: H03L 7/0898 the source or sink current values being variable H03L7/0896 takes precedence

Abstract

A capacitive charge pump that can be implemented in such devices as e.g. a phase locked loop (PLL). The charge pump includes at least one capacitor in the charge path and discharge path for limiting the amount of charge provided to or removed from a filter capacitor of a PLL. In one example, a second capacitor may be provided in the charge path or discharge path to reduce the capacitance (if provided in series) or increase the capacitance (if provided in parallel) to adjust the maximum amount of charge transferred to a filter capacitor. In one example, multiple capacitive stages may be implemented in parallel to increase the maximum amount of charge transferred to a filter capacitor. Each stage is enabled after a delayed period of time from when the previous stage was enabled.

Claims

1. A charge pump, comprising:

an output node;

a first capacitor having a first terminal coupled to a first circuit node; and

a first switch having a first current electrode coupled to the first circuit node, a control electrode coupled to receive a first switch control signal, and a second current electrode coupled to the output node, wherein the first switch control signal controls charge transfer between the first capacitor and the output node.

2. The charge pump of claim 1, wherein the output node is coupled to a filter capacitor that is significantly greater than the first capacitor.

3. The charge pump of claim 1, further comprising a potential setting circuit coupled to the first circuit node, wherein the potential setting circuit selectively sets, based on the first switch control signal, the first circuit node to a first potential.

4. The charge pump of claim 3, wherein the potential setting circuit includes a second switch having a control terminal coupled to receive an inverted signal of the first switch control signal, a second terminal coupled to a first voltage supply, and a third terminal coupled to the first circuit node.

5. The charge pump of claim 3, wherein the potential setting circuit has an input coupled to a node whose voltage is dependent upon a voltage of the output node and an output coupled to the first circuit node, wherein the first potential is dependent upon on the voltage of the output node.

6. The charge pump of claim 5 further comprising:

a comparator having a first input coupled the output node;

a current source coupled to an output of the comparator; and

a second switch having a first current electrode coupled to a second input of the comparator, a control electrode coupled to the output node, and a second current electrode coupled to the current source.

7. The charge pump of claim 1, wherein the first switch selectively couples the first capacitor to the output node in response to the first switch control signal.

8. The charge pump of claim 1, further comprising:

a second capacitor having a first terminal coupled to a terminal of the first capacitor and a second terminal coupled to a first voltage supply.

9. The charge pump of claim 8 wherein the second capacitor has and a second terminal coupled to a first voltage supply.

10. The charge pump of claim 8 wherein the first terminal of the second capacitor is coupled to the second terminal of the first capacitor.

11. The charge pump of claim 10, further comprising:

a third switch having a first current electrode coupled to the first terminal of the second capacitor, a second current electrode coupled to the first voltage supply, and a control electrode coupled to receive an enable signal, wherein the third switch selectively enables the second capacitor in response to the enable signal.

12. The charge pump of claim 8 further comprising:

a second switch having a first current electrode coupled to the first terminal of the second capacitor, a second current electrode coupled to the first voltage supply, and a control electrode coupled to receive an inverse of the first switch control signal.

13. The charge pump of claim 1, further comprising:

a second capacitor having a first terminal coupled to a second circuit node;

a second switch having a first current electrode coupled to the second circuit node, a second current electrode coupled to the output node.

14. The charge pump of claim 13, further comprising:

a delay circuit having an input coupled to receive the first switch control signal and an output coupled to a control electrode of the second switching circuit.

15. The charge pump of claim 13, further comprising:

a potential setting circuit coupled to the second circuit node and selectively sets, based on the first switch control signal, the second circuit node to a first potential.

16. The charge pump of claim 1, further comprising:

a second capacitor having a first terminal coupled to a second circuit node; and

a second switch having a first current electrode coupled to the second circuit node, a control electrode coupled to receive a second switch control signal, and a second current electrode coupled to the output node, wherein the second switch control signal controls charge transfer between the second capacitor and the output node.

17. The charge pump of claim 16, further comprising:

a first potential setting circuit coupled to the first circuit node, wherein the first potential setting circuit selectively sets, based on the first switch control signal, the first circuit node to a first potential.

a second potential setting circuit coupled to the second circuit node wherein the second potential setting circuit selectively sets, based on the second switch control signal, the second circuit node to a second potential, different from the first potential.

18. The charge pump of claim 16 wherein a second terminal of the first capacitor is coupled to a first voltage supply, wherein a second terminal of the second capacitor is coupled to a second voltage supply, different from the first voltage supply.

19. The charge pump of claim 16 wherein a second terminal of the first capacitor is coupled to a first voltage supply, wherein a second terminal of the second capacitor is coupled to the first voltage supply.

20. A phase locked loop circuit including the charge pump of claim 16, the phase locked loop circuit further comprising:

a filter capacitor having a first terminal coupled to the output node;

a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide the first switch control signal based on the first clock and the second clock and a second output to provide the second switch control signal based on the first clock and the second clock;

a voltage controlled oscillator having an input coupled to the output node and an output to provide an output clock.

21. The charge pump of claim 1, further comprising:

a second capacitor having a first terminal coupled to a first supply voltage;

a second switch having a control electrode coupled to receive the first switch control signal, a first current electrode coupled to a second terminal of the first capacitor, and a second current electrode coupled to a second terminal of the second capacitor wherein, the second switch selectively couples, based on the first switch control signal, the first capacitor and the second capacitor in series.

22. The charge pump of claim 21, wherein the first switch couples the first terminal of the first capacitor to the output node and the second switch couples the second terminal of the first capacitor to the second terminal of the second capacitor when the first switch control signal is at a first state.

23. The charge pump of claim 21, further comprising a third switch having a first current electrode coupled to the second terminal of the second capacitor, a second current electrode coupled to the output node, and a control electrode coupled to receive a second switch control signal.

24. The charge pump of claim 23, wherein the third switch selectively couples, based on the second switch control signal, the second terminal of the second capacitor to the output node.

25. The charge pump of claim 21, further comprising:

a first potential setting circuit coupled to the first capacitor, the potential setting circuit selectively setting, based on the first switch control signal, the first circuit node to a first potential;

a second potential setting circuit coupled to the second terminal of the second capacitor and selectively setting, based on the first switch control signal and a second switch control signal, the second terminal of the second capacitor to the first potential.

26. The charge pump of claim 25, wherein the first potential is based on a voltage of the output node.

27. The charge pump of claim 1 wherein the first switch includes a pass gate, the pass gate having a second control electrode coupled to receive an inverse of the first switch control signal.

31. The PLL circuit of claim 28, wherein the charge pump of claim 1, further comprises a second capacitor having a first terminal coupled to a terminal of the first capacitor and a second terminal coupled to a first voltage supply.

28. A phase locked loop (PLL) circuit comprising:

a filter capacitor;

a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide a first clock control signal based on the first clock and the second clock;

a voltage controlled oscillator having an input coupled to a first terminal of the filter capacitor and an output to provide an output clock;

a charge pump having a first input to receive the first clock control signal and an output coupled to the first terminal of the filter capacitor and the input of the voltage controlled oscillator, the charge pump comprising;

a first capacitor having a first terminal; and

a first switch having a first current electrode coupled to the first terminal of the first capacitor, a control electrode coupled to receive the first clock control signal, and a second current electrode coupled to the first terminal of the filter capacitor, the first switch selectively coupling the first capacitor to the filter capacitor, based on the first clock control signal.

29. The PLL circuit of claim 28, wherein the phase frequency detector circuit has a second output to provide a second clock control signal based on the first clock and the second clock, the charge pump further comprising:

a second capacitor;

a second switch having a first current electrode coupled to a first terminal of the second capacitor, a second current electrode coupled to the first terminal of the filter capacitor, and a control electrode coupled to receive the second clock control signal, the second switch selectively coupling the second capacitor to the filter capacitor, based on the second clock control signal.

30. The PLL circuit of claim 28, wherein the charge pump further comprises a potential setting circuit coupled to the first terminal of the first capacitor, wherein the potential setting circuit selectively sets, based on the first clock control signal, the first terminal of the first capacitor to a first potential.

32. The PLL circuit of claim 28 wherein the PLL circuit is implemented on an integrated circuit.

33. The PLL circuit of claim 32 wherein the first capacitor is implemented with as a metal capacitor.

34. The PLL circuit of claim 28 further comprising:

a frequency divider having an input to receive the output clock and an output to provide the second clock.

35. The PLL circuit of claim 28 wherein a filter capacitor that is significantly larger than the first capacitor.

36. A charge pump comprising:

an output node;

a charge path including a first capacitor;

a first switch including a control electrode coupled to receive a first charge control signal, wherein the first capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch;

a discharge path including a second capacitor;

a second switch having a control electrode coupled to receive a second charge control signal, wherein the second capacitor selectively receives charge, based on the second charge control signal, from the output node.

37. The charge pump of claim 36, further comprising:

a first potential setting circuit coupled to a first terminal of the first capacitor, wherein the first potential setting circuit selectively sets, based on the first charge control signal, the first terminal of the first capacitor to a first potential; and

a second potential setting circuit coupled to a first terminal of the second capacitor, wherein the second potential setting circuit selectively sets, based on the second charge control signal, the first terminal of the second capacitor to a second potential.

38. The charge pump of claim 37 wherein the first potential is equal to the second potential.

39. The charge pump of claim 37 wherein the first and second potentials are dependent upon a voltage of the output node.

40. The charge pump of claim 36, further comprising:

a third capacitor, wherein the third capacitor is coupled in series with the first capacitor, and wherein the first and third capacitors selectively provide charge, based on the first charge control signal and an enable signal, to the output node via the first switch; and

a fourth capacitor, wherein the fourth capacitor is coupled in series with the second capacitor, and wherein the second and fourth capacitors selectively receive charge, based on the second charge control signal and an enable signal, from the output node via the second switch.

41. The charge pump of claim 40, wherein:

when the enable signal has a first value, the first capacitor and not the third capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch, and

when the enable signal has a second value, the first capacitor and the third capacitor selectively provide charge, based on the first charge control signal, to the output node via the first switch.

42. The charge pump of claim 36, further comprising:

a third capacitor, the third capacitor selectively provides charge, based on a signal dependent upon the first charge control signal, to the output node;

a fourth capacitor, the fourth capacitor selectively receives charge, based on a signal dependent upon the second charge control signal, from the output node.

43. A phase locked loop circuit including the charge pump of claim 36, the phase locked loop circuit further comprising:

a filter capacitor having a first terminal coupled to the output node;

a phase frequency detector circuit having a first input to receive a first clock, a second input to receive a second clock, and a first output to provide the first charge control signal based on the first clock and the second clock and a second output to provide the second charge control signal based on the first clock and the second clock;

a voltage controlled oscillator having an input coupled to the output node and an output to provide an output clock.

44. The charge pump of claim 36, further wherein:

the first switch has a first current electrode coupled to a first terminal of the first capacitor and has a second current electrode coupled to the output node;

the first capacitor selectively provides charge, based on the first charge control signal, to the output node via the first switch;

the second switch has a first current electrode coupled to a first terminal of the second capacitor and has a second current electrode coupled to the output node;

the second capacitor selectively receives charge, based on the second charge control signal, from the output node via the second switch.