Display controller
First Claim
Patent Images
1. A method for controlling a display device having a scan line rate, comprising storing incoming data in a buffer, the buffer having a usage level measure;
- comparing the usage level to the scan line rate; and
adjusting a period of the scan line to avoid buffer overflow or underflow.
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Accused Products
Abstract
Systems and methods are disclosed for controlling a display device having a display scan line rate by storing incoming data in a buffer, the buffer having a usage level measure; comparing the usage level to the display scan line rate; and adjusting a width of a display scan line to avoid buffer overflow or underflow. The system avoids a costly external frame buffer and automatically handles uncertainties such as jitter in input and output clocks when the system operates in different environments.
62 Citations
20 Claims
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1. A method for controlling a display device having a scan line rate, comprising
storing incoming data in a buffer, the buffer having a usage level measure; -
comparing the usage level to the scan line rate; and
adjusting a period of the scan line to avoid buffer overflow or underflow. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 18)
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11. A controller for a digital display, comprising:
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a buffer to receive image data, the buffer having a usage level measure;
a timing controller to drive the display having a scan line rate; and
a buffer controller coupled to the buffer and the timing controller, the buffer controller snooping the usage level of the buffer, comparing the usage level to the scan line rate, and adjusting a scan line rate to avoid buffer overflow or underflow. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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19. A method for controlling a liquid crystal display (LCD) panel with an LCD horizontal sync (HSYNC) signal, comprising:
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storing incoming data in a buffer, the buffer having a usage level measure;
comparing the usage level to the HSYNC signal; and
adjusting a period of the HSYNC signal to avoid buffer overflow or underflow.
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20. A liquid crystal display (LCD) controller, comprising:
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a buffer to receive image data, the buffer having a usage level measure;
an interpolation/decimation engine coupled to the buffer, the interpolation/decimation engine minimizing diagonal image jaggedness;
a timing controller coupled to the interpolation/decimation engine;
a buffer controller coupled to the buffer, the interpolation/decimation engine and the timing controller, the buffer control circuit snooping the usage level of the buffer, comparing the usage level to an LCD horizontal sync (HSYNC) signal, and adjusting the HSYNC period to avoid buffer overflow or underflow; and
a post-processing circuit coupled to the interpolation/decimation engine and the timing controller.
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Specification