High voltage low power sensing device for flash memory
First Claim
1. A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises:
- a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter having an input and an output for providing an output signal indicative of a potential level of the input of the sense inverter relative to a threshold point;
a precharge path coupled to the input of the sense inverter for providing a precharge potential to the input of the sense inverter;
a feedback loop interposed between the precharge path and the input node of the sensing device, wherein the feedback loop limits a potential level on the input node of the sensing device to a predetermined maximum potential level; and
a reference current path coupled to the input of the sense inverter for providing a reference current to the input of the sense inverter.
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Abstract
Sensing devices for sensing a programmed state of a floating-gate memory cell are adapted for use in low-power memory devices using supply potentials that can be significantly higher than the maximum potential to be achieved on a local bit line during a sensing operation. Such sensing devices include an input node selectively coupled to a floating-gate memory cell and an output node for providing an output signal indicative of the programmed state of the floating-gate memory cell. Such sensing devices further include a feedback loop coupled between a precharge path and the input node of the sensing device. The feedback loop limits the potential level achieved at the input node of the sensing device, thus limiting the potential level achieved by the bit lines during sensing.
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Citations
28 Claims
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1. A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises:
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter having an input and an output for providing an output signal indicative of a potential level of the input of the sense inverter relative to a threshold point;
a precharge path coupled to the input of the sense inverter for providing a precharge potential to the input of the sense inverter;
a feedback loop interposed between the precharge path and the input node of the sensing device, wherein the feedback loop limits a potential level on the input node of the sensing device to a predetermined maximum potential level; and
a reference current path coupled to the input of the sense inverter for providing a reference current to the input of the sense inverter. - View Dependent Claims (2, 3, 4, 5)
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6. A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises:
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal; and
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter. - View Dependent Claims (7, 8)
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9. A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises:
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal;
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter;
a fifth p-channel field-effect transistor coupled between the first potential node and the second p-channel field-effect transistor and having a gate coupled to receive the enable signal;
a third n-channel field-effect transistor coupled between the input of the sense inverter and a fourth potential node and having a gate coupled to receive the enable signal; and
a fourth n-channel field-effect transistor coupled between the input node of the sensing device and a fifth potential node and having a gate coupled to receive the enable signal. - View Dependent Claims (10, 11, 12)
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13. A flash memory device having an array of floating-gate memory cells, wherein the flash memory device comprises:
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal;
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter;
a p-channel stage having a source coupled to a fourth potential node, a drain coupled to an output node of the sensing device and a gate coupled to the input of the sense inverter; and
an n-channel stage having a source coupled to a fifth potential node, a drain coupled to the output node and a gate coupled to the input of the sense inverter. - View Dependent Claims (14)
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15. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, the memory device having an array of floating-gate memory cells, wherein the memory device further comprises;
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter having an input and an output for providing an output signal indicative of a potential level of the input of the sense inverter relative to a threshold point;
a precharge path coupled to the input of the sense inverter for providing a precharge potential to the input of the sense inverter;
a feedback loop interposed between the precharge path and the input node of the sensing device, wherein the feedback loop limits a potential level on the input node of the sensing device to a predetermined maximum potential level; and
a reference current path coupled to the input of the sense inverter for providing a reference current to the input of the sense inverter. - View Dependent Claims (16, 17, 18, 19)
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20. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, the memory device having an array of floating-gate memory cells, wherein the memory device further comprises;
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal; and
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter. - View Dependent Claims (21, 22)
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23. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, the memory device having an array of floating-gate memory cells, wherein the memory device further comprises;
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal;
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter;
a fifth p-channel field-effect transistor coupled between the first potential node and the second p-channel field-effect transistor and having a gate coupled to receive the enable signal;
a third n-channel field-effect transistor coupled between the input of the sense inverter and a fourth potential node and having a gate coupled to receive the enable signal; and
a fourth n-channel field-effect transistor coupled between the input node of the sensing device and a fifth potential node and having a gate coupled to receive the enable signal. - View Dependent Claims (24, 25, 26)
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27. An electronic system, comprising:
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a processor; and
a memory device coupled to the processor, the memory device having an array of floating-gate memory cells, wherein the memory device further comprises;
a single-ended sensing device for sensing a programmed state of a floating-gate memory cell, wherein the sensing device has an input node selectively coupled to a floating-gate memory cell, the sensing device further comprising;
a sense inverter;
a first p-channel field-effect transistor coupled between a first potential node and an input of the sense inverter;
a second p-channel field-effect transistor coupled between the first potential node and the input of the sense inverter;
a first n-channel field-effect transistor coupled between the input of the sense inverter and the input node of the sensing device;
a second n-channel field-effect transistor having a gate coupled to the input node of the sensing device, a drain coupled to a gate of the first n-channel field-effect transistor and a source coupled to a second potential node;
a third p-channel field-effect transistor coupled between a third potential node and the gate of the first n-channel field-effect transistor, wherein the third p-channel field-effect transistor has a gate coupled to receive an enable signal;
a fourth p-channel field-effect transistor coupled between the third potential node and the gate of the first n-channel field-effect transistor, wherein the fourth p-channel field-effect transistor has a gate coupled to receive the enable signal through an inverter;
a p-channel stage having a source coupled to a fourth potential node, a drain coupled to an output node of the sensing device and a gate coupled to the input of the sense inverter; and
an n-channel stage having a source coupled to a fifth potential node, a drain coupled to the output node and a gate coupled to the input of the sense inverter. - View Dependent Claims (28)
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Specification