Very low effective dielectric constant interconnect Structures and methods for fabricating the same

• US 20040087135A1
• Filed: 10/24/2002
• Published: 05/06/2004
• Est. Priority Date: 10/24/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy J., Purushothaman, Sampath, Nitta, Satya V., Gates, Stephen M., Krishnan, Mahadevaiyer, Canaperi, Donald F., Smith, Sean P.E.
• Granted Patent: US 7,023,093 B2
• Time in Patent Office: Days
• US Class Current: 438/628
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.

Claims

1. An etch back and gap fill method for fabricating an interconnect structure in an integrated circuit comprising the steps of:

a) Depositing a support dielectric on a supporting surface;

b) Forming a set of interconnect apertures in said support dielectric, at least some of which apertures have a lower surface separated by a vertical distance from said supporting surface;

c) Forming a set of wiring features by filling said set of interconnect apertures with an electrically conductive interconnect material and planarizing such that the top surface of said wiring features are substantially coplanar with the top surface of said support dielectric, whereby at least some of said wiring features are supported by a supporting portion of said support dielectric below said lower surface;

d) Etching said support dielectric with a directional etch using said wiring features as a mask, such that the support dielectric is only left in the structure in said supporting portions underneath said wiring features; and

e) depositing a gap fill dielectric material over said set of wiring features such that the gaps between said set of wiring features are filled with said gap fill dielectric; and

f) Planarizing said gap fill dielectric until the top surface of said set of wiring features is substantially coplanar with the top surface of said gap fill dielectric.

2. A method according to claim 1, in which said step of planarizing said gap fill dielectric is carried out by chemical-mechanical polishing.

3. A method according to claim 1, in which said step of

planarizing said gap fill dielectric further comprises an etching process comprising a first etching process and a second etching process less aggressive than said first etching process;

monitoring said first etching process with an end point detection system and changing to said second etching process before said set of wiring features is exposed; and

continuing said second etching process until the top surface of said set of wiring features is substantially coplanar with the top surface of said gap fill dielectric.

4. A method according to claim 2, further comprising a step of

depositing a conformal encapsulating layer over said set of wiring features before said step of depositing a gap fill dielectric.

5. A method according to claim 4, in which the material of said encapsulating layer blocks oxygen and copper, whereby copper interconnect material is confined within said wiring features and oxygen is excluded from said wiring features.

6. A method according to claim 5, in which the material of said encapsulating layer is selected from the group comprising SiCH, SiNCH, Si3N4, SiCOH, and SiO2.

7. A method according to claim 3, in which said monitoring is performed by an interferometry system that emits an etch change signal when the thickness of said gap fill dielectric over said wiring features is less than a reference amount, whereby said first etching process is stopped and said second etching process is started in response to said etch change signal.

8. The method according to claim 2, wherein said gap fill dielectric is selected from the group comprising both solid and porous:

spin on glasses including at least methyl silsesquioxane, hydrido silsesquioxane, and mixed silsesquioxanes;

amorphous hydrogenated dielectric films including silicon and at least one of carbon, hydrogen, oxygen and nitrogen;

spin on organic dielectrics including at least polyimides, benzocyclobutene, polybenzoxadoles and aromatic thermoset polymers based on polyphenylene ethers;

chemical vapor deposited polymers including at least poly paraxylylene; and

combinations thereof.

9. A method according to claim 3, further comprising a CMP step performed before said step of planarizing said gap fill dielectric by etching.

10. A structure comprising a substrate having at least one interconnect layer disposed thereabove, said interconnect layer comprising a set of conductive vias and a set of conductive horizontal interconnect members disposed above said set of vias and connected thereto, wherein said horizontal interconnect members are supported by a support dielectric having a first dielectric constant and extending vertically from a lower surface of said set of vias to a lower surface of said horizontal interconnect members and extending horizontally under said horizontal interconnect members;

and

a gap fill dielectric, having a second dielectric constant lower in value than said first dielectric constant, filling gaps between said set of horizontal interconnect members.

11. A structure according to claim 10, wherein the substrate is selected from the group comprising a semiconductor device chip and a chip carrier.

12. A structure according to claim 10, wherein said horizontal interconnect members comprise a conductive barrier material and a highly conducting fill material and wherein said conducting barrier material is selected from the group comprising Ti, Ta, Cr, W, Zr, Hf;

and their conductive oxides, nitrides, oxynitrides, carbo-nitrides, and silico-nitrides.

13. A structure according to claim 12, wherein said highly conductive fill material is selected from the group comprising Cu, Al, Au and W.

14. A structure according to claim 10, wherein said support dielectric material is selected from the group comprising both solid and porous:

silicon dioxide, fluorinated silicon oxide;

amorphous hydrogenated dielectric films comprising silicon and at least one of carbon, oxygen, hydrogen and nitrogen;

spin on glass films prepared from tetraethyl orthosilicate, methyl silsesquioxane, hydrido silsesquioxane, and mixed silsesquioxanes;

diamond like carbon;

spin on organic dielectrics including at least one of polyimides, benzocyclobutene, polybenzoxazoles and aromatic thermoset polymers based on polyphenylene ethers; and

chemical vapor deposited polymers including at least poly paraxylylene.

15. A structure according to claim 10, wherein said lower dielectric constant gap fill dielectric is different from said support dielectric and selected from the group comprising both solid and porous:

spin on glasses including at least methyl silsesquioxane, hydrido silsesquioxane, and mixed silsesquioxanes;

amorphous hydrogenated dielectric films comprising silicon and at least one of carbon, hydrogen, oxygen and nitrogen;

spin on organic dielectrics including at least polyimides, benzocyclobutene, polybenzoxadoles, aromatic thermoset polymers based on polyphenylene ethers; and

chemical vapor deposited polymers including at least poly paraxylylene.

16. A structure according to claim 10, in which said cap layer is formed only over said set of horizontal interconnect members.

17. A structure according to claim 16, wherein said cap layer is chosen from the group comprising:

(a) amorphous hydrogenated insulator films of silicon nitride, silicon carbide, silicon carbonitride;

(b) Ti, Ta, Cr, W, Zr, Hf, their conductive oxides, nitrides, oxynitrides, carbo-nitrides, silico-nitrides, and combinations thereof;

(c) alloys of Co—

W—

P, Co—

Sn—

P, Co—

Ni—

P, and Co—

P; and

(d) combinations of insulating films from group (a) and conducting films from groups (b) and (c).

18. A structure according to claim 10, further comprising a cap layer covering the top surface of said horizontal interconnect members and said gap fill dielectric.

19. A structure according to claim 18, wherein a first cap layer is formed only on the top surface of said horizontal interconnect members and a second cap layer is formed on the top surface of said gap fill dielectric and on the top surface of said horizontal interconnect members.

20. A structure according to claim 19 , wherein said first cap layer is chosen from the group comprising:

(a) amorphous hydrogenated insulator films of silicon nitride, silicon carbide, silicon carbonitride;

(b) Ti, Ta, Cr, W, Zr, Hf, their conductive nitrides, oxides, oxynitrides, carbo-nitrides, silico-nitrides, and combinations thereof;

(c) alloys of Co—

W—

P, Co—

Sn—

P, Co—

Ni—

P, and Co—

P; and

(d) combinations of insulating films from group (a) and conducting films from groups (b) and (c).

21. A structure according to claim 19, wherein said second cap layer is chosen from the group comprising:

amorphous hydrogenated insulator films of silicon nitride, silicon carbide and silicon carbonitride.

22. A multilevel structure according to claim 10, comprising a substrate with at least two wiring layers disposed on top of each other, with a final level of interconnect wiring layer wherein the wires and vias are surrounded fully by a second support dielectric.

23. The structure of claim 22, wherein said second support dielectric is selected from the group comprising silicon dioxide, fluorinated silicon oxide;

amorphous hydrogenated dielectric films comprising at least one of silicon, carbon, oxygen, hydrogen and nitrogen;

spin on glass films prepared from tetraethyl orthosilicate, methyl silsesquioxane, hydrido silsesquioxane, and mixed silsesquioxanes;

diamond like carbon;

spin on organic dielectrics including at least polyimides, benzocyclobutene, polybenzoxazoles, aromatic thermoset polymers based on polyphenylene ethers;

chemical vapor deposited polymers including at least poly paraxylylene; and

combinations thereof.

24. A structure according to claim 10, in which said support dielectric extends transversely across said set of conductive vias and said set of conductive horizontal interconnect members, whereby said gap fill dielectric fills gaps between said horizontal interconnect members only above said support dielectric.

25. A structure according to claim 24 in which the top surface of said support dielectric is located between the bottom surface of said conductive horizontal interconnect members and the bottom surface said set of conductive vias.

26. A structure according to claim 10, in which said support dielectric extends transversely under said set of conductive horizontal interconnect members, whereby said gap fill dielectric fills gaps between said horizontal interconnect members down to the level of said upper surface of said set of vias.