Low latency frequency switching

• US 20040087292A1
• Filed: 04/24/2003
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Zhang, Li, Shiu, Da-shan, Sy, Eugene
• Granted Patent: US 7,307,480 B2
• Time in Patent Office: Days
• US Class Current: 455/232.1
• CPC Class Codes: H03G 3/3036 in high-frequency amplifiers or in frequency-changers H03G3/3052, H03G3/32, H03G3/34 take precedence

Abstract

Techniques for improved low latency frequency switching are disclosed. In one embodiment, a controller receives a frequency switch command and generates a frequency switch signal at a time determined in accordance with a system timer. In another embodiment, gain calibration is initiated subsequent to the frequency switch signal delayed by the expected frequency synthesizer settling time. In yet another embodiment, DC cancellation control and gain control are iterated to perform gain calibration, with signaling to control the iterations without need for processor intervention. Various other embodiments are also presented. Aspects of the embodiments disclosed may yield the benefit of reducing latency during frequency switching, allowing for increased measurements at alternate frequencies, reduced time spent on alternate frequencies, and the capacity and throughput improvements that follow from minimization of disruption of an active communication session and improved neighbor selection.

Claims

1. A first Integrated Circuit (IC), responsive to a frequency switch signal generated in a second IC, the second IC comprising a timer to generate a timing reference and a controller to receive a frequency switch command and generate the frequency switch signal in response to the frequency switch command and the timing reference, the first IC comprising:

a frequency synthesizer to receive a frequency switch signal from the second IC and to generate an output signal, the frequency of the output signal changing from a first frequency to a second frequency in response to the frequency switch signal.

2. A first Integrated Circuit (IC), responsive to at least one of one or more Direct Current (DC) offset values and one or more gain values generated in a second IC, the second IC comprising:

a DC cancellation controller to;

receive a first signal;

determine the one or more DC offset values in response to a received communication signal subsequent to an assertion on the first signal; and

generate a second signal indicating the one or more DC offset values determination is complete; and

a gain controller to;

receive the second signal;

determine the one or more gain values in response to the received communication signal subsequent to an assertion on the second signal; and

generate the first signal indicating the one or more gain values determination is complete,

the first IC comprising at least one of;

a DC canceller to receive the one or more DC offset values from the second IC and to cancel a component of a received signal in response to the one or more DC offset values to produce a DC cancelled signal; and

one or more gain stages to receive the one or more gain values from the second IC and to adjust the gain of a received signal in response to the one or more gain values to produce a gain adjusted signal.

3. An apparatus, operable with a frequency synthesizer, comprising:

a timer to generate a timing reference; and

a controller to receive a frequency switch command and generate a frequency switch signal in response to the frequency switch command and the timing reference.

4. The apparatus of claim 3, further comprising means for transmitting the frequency switch signal to the frequency synthesizer on a shared bus.

5. The apparatus of claim 4, wherein frequency parameters are transmitted to the frequency synthesizer on the shared bus coincident with the frequency switch signal.

6. The apparatus of claim 3, further comprising a processor for generating frequency switch commands.

7. The apparatus of claim 6, wherein a frequency switch command includes at least one of a switching time and frequency parameters.

8. The apparatus of claim 6, wherein the processor further generates calibration initiation commands.

9. The apparatus of claim 3, further comprising a calibration initiation timer to receive a synthesizer settling time parameter and the frequency switch signal and generate a calibration initiation signal delayed from the frequency switch signal in response to the synthesizer settling time parameter.

10. The apparatus of claim 9, further comprising a direct current (DC) cancellation controller to determine one or more DC offset calibration values in response to a received signal, the one or more DC offset calibration values determination being initiated in response to the calibration initiation signal.

11. The apparatus of claim 3, further comprising a DC cancellation controller to:

determine one or more DC offset values in response to a received signal;

receive a calibration initiation command; and

initiate the one or more DC offset calibration values determination in response to the calibration initiation command and the timing reference.

12. The apparatus of claim 11, wherein the calibration initiation command includes a calibration start time computed in response to a frequency switch start time included in the frequency switch command and a synthesizer settling time parameter.

13. An apparatus, comprising:

a DC cancellation controller to;

receive a first signal;

determine one or more DC offset values in response to a received communication signal subsequent to an assertion on the first signal; and

generate a second signal indicating the one or more DC offset values determination is complete; and

a gain controller to;

receive the second signal;

determine one or more gain values in response to the received communication signal subsequent to an assertion on the second signal; and

generate the first signal indicating the one or more gain values determination is complete.

14. The apparatus of claim 13, wherein the DC cancellation controller further receives a third signal indicating the received communication signal is ready for DC cancellation and determines the one or more DC offset values subsequent to an assertion on the third signal.

15. The apparatus of claim 13, wherein the gain controller further generates a fourth signal indicating that DC offset value determination and gain value determination are complete.

16. A method of frequency switching, comprising:

receiving a frequency switch command including a frequency switch time;

generating a frequency switch signal in accordance with the frequency switch time and a timing reference; and

transmitting the frequency switch signal to a frequency synthesizer.

17. The method of claim 16, further comprising initiating gain calibration subsequent to an assertion on the frequency switch signal.

18. A method of gain calibration, comprising:

waiting for a gain adjustment complete signal or a gain calibration initiation signal;

measuring a DC component of a received signal;

applying one or more offsets to cancel the measured DC component; and

generating a DC calibration stage complete signal subsequent to offset application.

19. The method of claim 18, further comprising:

waiting for a DC calibration stage complete signal;

measuring a gain estimate of a received signal;

applying one or more gain values to adjust the gain of the received signal; and

generating a gain adjustment complete signal subsequent to the gain value application.

20. The method of claim 19, wherein a gain value is applied to a Low Noise Amplifier (LNA) by selecting one of a plurality of LNA gain values.

21. The method of claim 20, further comprising:

iterating the DC calibration and gain adjustment steps until the measured gain estimate falls within a pre-determined threshold;

measuring an additional gain estimate of the received signal;

applying a gain value to a Variable Gain Amplifier (VGA) to adjust the received signal in response to the additional gain estimate; and

generating a calibration complete signal.

22. The method of claim 21, further comprising searching the received signal subsequent to an assertion on the calibration complete signal.