Auto classification shipping system

• US 20040088074A1
• Filed: 11/02/2002
• Published: 05/06/2004
• Est. Priority Date: 11/02/2002
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yu-Chih, Hsieh, Remaerd
• Granted Patent: US 7,079,960 B2
• Time in Patent Office: Days
• US Class Current: 700/223
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2029/5606 Error catch memory
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A new method and system of testing and classifying semiconductor devices is provided. User requirements are collected for this purpose, test specifications and test functions are defined for the to be tested DRAM devices. The Automatic Classification Shipping (ACS) data base is updated with test related data, the testing is performed whereby DRAM devices are assigned categories from with DRAM classes are derived. These identified classes are used to sort the tested DRAM devices in accordance with their tested functional performance characteristics.

Claims

1. A method for sorting semiconductor devices in support of an Automatic Classification Shipping function, comprising the steps of:

entering user requirements into a supporting data base storage, said user requirements comprising a biasing factor Θ

;

entering wafer and chip logistics data into the supporting data base storage, said logistics data being required for control of wafer and chip product flow;

entering a chip testing data into the supporting data base storage, thereby including test criteria, said test criteria being divided into a range of acceptable test result values, said range of acceptable test result values having a high limit value and a low limit value, said chip test criteria further comprising a test biasing factor;

positioning said chip in a chip tester device to perform at least one test on said chip, thereby obtaining a test result;

calculating at least one weight point for said at least one test, said calculation being based on comparing said test result with said high limit value or said low limit value;

providing at least two chip classes;

dividing said at least one chip class into at least one multiple chip class.

2. The method of claim 1, said user requirements comprising:

wafer lot number or Identification Number (ID);

wafer number or Identification Number (ID) within wafer lot number;

at least one chip class number;

at least one chip class name;

at least one category number; and

at least one category name.

3. The method of claim 1, said chip logistics data comprising:

wafer routing data; and

chip location data within wafer number.

4. The method of claim 1, said high limit value being “

spechi”

, said low limit value being “

speclo”

, said test result being “

value”

, said test biasing value being Θ

, said weight point being “

Y”

, calculating a weight point “

Y”

comprising;

calculating Y=|(“

value”

−

“

speclo”

)/“

speclo”

|−

Θ

for condition of “

value”

≦

“

speclo”

;

or calculating Y=0 for condition of “

speclo”

≦

“

value”

≦

“

spechi”

;

or

calculating Y=|(“

value”

−

“

spechi”

)/“

spechi”

|−

Θ

for condition of “

value’

>

“

spechi”

.

5. The method of claim 1, said dividing said at least one chip class into at least one multiple chip class comprising sorting said at least one chip class in numerically incrementing values.

6. The method of claim 1, said chips comprising DRAM devices.

43. The method of claim 1, additionally adding said calculated at least one weight point “

Y”

for said at least one test, creating at least one chip class.

7. A method of sorting “

m”

semiconductor chips created over the surface of one wafer having a wafer Identification Number (wafer ID) into “

c”

classes by performing “

n”

tests per chip, said semiconductor chips being designated by a variable “

i”

having a range from “

1”

through “

m”

, said classes being designated by a variable “

k”

having a range from “

1”

through “

c”

, said tests being designated by a variable “

j”

having a range from “

1”

through “

n”

, comprising steps of;

branching into a software routine written in support of said method of sorting “

m”

semiconductor chips from a supervisory routine;

entering user requirements into a supporting data base storage, said user requirements comprising a test biasing factor Θ

[j], said user requirements further comprising a value for “

m”

, a value for “

j” and

a value for “

k”

;

entering wafer ID and chip ID logistics data into a supporting data base storage, said logistics data being required for control of product flow of said wafer ID and “

m”

chips having a chip ID created over the surface thereof;

entering chip testing data for testing of “

m”

chips into a supporting data base storage, thereby including test criteria, said test criteria being divided into a range of acceptable test result values, said range of acceptable test result values having a high limit value and a low limit value for each test “

j”

performed on chip “

i”

;

positioning said wafer in a chip tester device;

setting “

i”

equal to “

1”

;

setting “

j”

equal to “

1”

;

providing said chip tester device with said testing data for said chip “

i”

;

performing test “

j”

on said chip, thereby obtaining test result value;

calculating an “

j”

^th weight point for said test “

j”

based on said comparing said test result value with said spec high limit value and said spec low limit value

incrementing “

j”

by the numeric value of “

1”

;

evaluating a value of “

j”

, for;

(i) “

j”

≦

“

n”

, resume processing of performing test “

j”

on said chip, thereby obtaining test result value for test “

j”

;

(ii) for “

j”

>

“

n”

;

summarizing “

j”

^th weight points with “

j”

varying from “

1”

through “

j”

;

subtracting a testing biasing factor Θ

[j] assigned to said test “

j”

from said summarized “

j”

^th weight points;

assigning a class C[i] to said chip “

i”

based on results obtained by said subtracting a weight point Θ

[j] assigned to said test “

j”

from said summarized “

j”

^th weight points;

incrementing “

i”

by the numeric value of “

1”

;

evaluating a value of “

i”

, for;

(i) “

i”

≦

“

m”

, resume processing of performing test “

j”

on said chip, thereby obtaining test result;

(ii) for “

i”

>

“

m”

, and;

returning to said supervisory routine by branching to said supervisory routine.

8. The method of claim 7, said user requirements comprising:

wafer lot number;

wafer number within wafer lot number;

at least one chip class number;

at least one chip class name;

at least one category number; and

at least one category name.

9. The method of claim 7, said chip logistics data comprising:

wafer routing data; and

chip location data within wafer number.

10. The method of claim 7, said test result value for each test “

j”

performed on chip “

i”

being “

value[i,j]”

, said high limit value for each test “

j”

performed on chip “

i”

being spechi[i,j]”

, said a low limit value for each test “

j”

performed on chip “

i”

being “

speclo[i,j]”

, said weight point for each test “

j”

performed on chip “

i”

being Y[i,j], said calculating a weight point “

Y[i,j]”

for each test “

j”

performed on chip “

i”

comprising;

calculating Y[i,j]=|(“

value[i,j]”

−

“

speclo[i,j”

)/“

speclo[i,j”

|−

Θ

[i] for condition of “

value[i,j]”

≦

“

speclo[i,j]”

;

or

calculating Y[i,j]=0 for condition of “

speclo[i,j]”

≦

“

value[i,j]”

≦

“

spechi[i,j]”

;

or

calculating Y[i,j]=|(“

value[i,j]”

−

“

spechi[i,j]”

)/“

spechi[i,j]”

|−

Θ

[i] for condition of “

value(i,j]”

>

“

spechi[i,j]”

.

11. The method of claim 7, said dividing said chip class C[i] into at least one multiple chip class comprising sorting said at least one chip class in numerically incrementing values.

12. The method of claim 7, said chips comprising DRAM devices.

13. The method of claim 7, further extending this method to assigning a class designation to said wafer ID using the steps of:

determining a maximum value of said chip class C[i], creating a value of max C[i]; and

assigning said value of max C[i] to said wafer ID, creating a wafer class W[w].

14. The method of claim 13, further extending this method to assigning a class designation to a wafer lot having a lot ID, said lot ID comprising multiple said wafer ID, using the steps of:

summarizing said C[i] within a wafer ID for each value of “

i”

, creating a sum [i];

selecting a maximum value of sum[i], creating a max sum[i]; and

assigning said max sum[i] to said lot ID.

15. A method for sorting semiconductor devices in support of an Automatic Classification Shipping function, comprising the steps of:

testing said semiconductor devices by applying “

n”

tests to said devices thereby obtaining a test result value, said testing comprising assigning a high limit value and a low limit value to device test criteria, further comprising assigning a test biasing factor;

calculating a weight point for each test based on test results obtained;

adding all calculated weight points for a semiconductor device, creating a Summary of Weight Points for a semiconductor device;

assigning a class to said semiconductor device based on said Summary of Weight Points; and

sorting said classes assigned to said semiconductor devices Summary in numerical sequence.

16. The method of claim 15, said test result value being “

value”

, said high limit value being “

spechi”

, said low limit value being “

speclo”

, said test biasing value being Θ

, said calculating a weight point “

Y”

comprising;

calculating Y=|(“

value”

−

“

speclo”

)/“

speclo”

|−

Θ

for condition of “

value”

≦

“

speclo”

;

or

calculating Y=0 for condition of “

speclo”

≦

“

value”

≦

“

spechi”

;

or

calculating Y=|(“

value]”

−

“

spechi”

)/“

spechi”

|−

Θ

for condition of “

value”

>

“

spechi”

.

17. The method of claim 15, said semiconductor devices comprising DRAM devices.

18. The method of claim 15, said method being applied to sorting semiconductor devices created over the surface of one wafer.

19. The method of claim 15, said method being applied to sorting semiconductor devices created over the surface of multiple wafers.

20. The method of claim 19, said method further being extended to assigning a wafer class to individual wafers having a wafer ID of said multiple wafers, said extension comprising steps of identifying the class that is maximally assigned to semiconductor devices created over the surface of one wafer having a wafer ID and assigning this class to said wafer ID.

21. The method of claim 20, said method further being extended to assigning a lot class to individual lots having a lot ID comprising said multiple wafers, said extension comprising steps of identifying the class that is maximally assigned to wafers pertaining to said lot ID and assigning this class to said lot ID.

22. A system for sorting semiconductor devices in support of an Automatic Classification Shipping function, comprising:

means for entering user requirements into a supporting data base storage, said user requirements comprising a biasing factor Θ

;

means for entering wafer and chip logistics data into a supporting data base storage, said logistics data being required for control of wafer and chip product flow;

means for entering chip testing data into a supporting data base storage, thereby including test criteria, said test criteria being divided into a range of acceptable test result values, said range of acceptable test result values having a high limit value and a low limit value said chip test criteria further comprising a test biasing factor;

means for positioning said chip in a chip tester device;

means for providing said chip tester device with said testing data for said chip;

means for performing at least one test on said chip, thereby obtaining a test result value;

means for calculating at least one weight point “

Y”

for said at least one test, said calculation being based on comparing said test result value with said high limit and said low limit; and

means for dividing said at least one chip class into at least one multiple chip class.

23. The system of claim 22, said user requirements comprising:

wafer lot number or Identification Number (ID);

wafer number or Identification Number (ID) within wafer lot number;

at least one chip class number;

at least one chip class name;

at least one category number; and

at least one category name.

24. The system of claim 22, said chip logistics data comprising:

wafer routing data; and

chip location data within wafer number.

25. The system of claim 22, said test result value being “

value”

, said high limit being “

spechi”

, said low limit being “

speclo”

, said biasing value being Θ

, said means for calculating a weight point “

Y”

comprising;

means for calculating Y=|(“

value”

−

“

speclo”

)/“

speclo”

|−

Θ

for condition of “

value”

≦

“

speclo”

;

or

means for calculating Y=0 for condition of “

speclo”

≦

“

value”

≦

“

spechi”

;

or

means for calculating Y=|(“

value”

−

“

spechi”

)/“

spechi”

|−

Θ

for condition of “

value’

>

“

spechi”

.

26. The system of claim 22, said means for dividing said at least one chip class into at least one multiple chip class comprising means for sorting said at least one chip class in numerically incrementing values.

27. The system of claim 22, said chips comprising DRAM devices.

44. The system of claim 22, additionally comprising means for adding said calculated at least one weight point “

Y”

for said at least one test, creating at least one chip class.

28. A system of sorting “

m”

semiconductor chips created over the surface of one wafer having a wafer Identification Number (wafer ID) into “

c”

classes by performing “

n”

tests per chip, said semiconductor chips being designated by a variable “

i”

having a range from “

1”

through “

m”

, said classes being designated by a variable “

k”

having a range from “

1”

through “

c”

, said tests being designated by a variable “

j”

having a range from “

1”

through “

n”

, comprising;

means for branching into a software routine written in support of said method of sorting “

m”

semiconductor chips from a supervisory routine;

means for entering user requirements into a supporting data base storage, said user requirements comprising a test biasing factor, said user requirements further comprising a value for “

m”

, a value for “

j” and

a value for “

k”

;

means for entering wafer ID and chip ID logistics data into a supporting data base storage, said logistics data being required for control of product flow of said wafer ID and “

m”

chips having a chip ID created over the surface thereof;

means for entering chip testing data for testing of “

m”

chips into a supporting data base storage, thereby including test criteria, said test criteria being divided into a range of acceptable test result values, said range of acceptable test result values having a high limit value and a low limit value for each test “

j”

performed on chip “

i”

;

means for positioning said wafer in a chip tester device;

means for setting “

i”

equal to “

1”

;

means for setting “

j”

equal to “

1”

;

means for providing said chip tester device with said testing data for said chip “

i”

;

means for performing test “

j”

on said chip, thereby obtaining test result value;

means for calculating an “

j”

^th weight point for said test “

j”

based on said comparing said test result value with said high limit value and said low limit value;

means for incrementing “

j”

by the numeric value of “

1”

;

means for evaluating a value of “

j”

, for;

(i) “

j”

≦

“

n”

, resume processing of performing test “

j”

on said chip, thereby obtaining test result value;

(ii) for “

j”

>

“

n”

;

means for summarizing “

j”

^th weight points with “

j”

varying from “

1”

through “

j”

;

means for subtracting a test biasing value assigned to said test “

j”

from said summarized “

j”

^th weight points;

means for assigning a class C[i] to said chip “

i”

based on results obtained by said subtracting test biasing value assigned to said test “

j”

from said summarized “

j”

^th weight points;

means for incrementing “

i”

by the numeric value of “

1”

;

means for evaluating a value of “

i”

, for;

(i) “

i”

≦

“

m”

, resume processing of performing test “

j”

on said chip, thereby obtaining test result value;

(ii) for “

i”

>

“

m”

, and;

means for returning to said supervisory routine by branching to said supervisory routine.

29. The system of claim 28, said user requirements comprising:

wafer lot number;

wafer number within wafer lot number;

at least one chip class number;

at least one chip class name;

at least one category number; and

at least one category name.

30. The system of claim 28, said chip logistics data comprising:

wafer routing data; and

chip location data within wafer number.

31. The system of claim 28, said high limit value being “

spechi[i,j]” and

said low limit value being “

speclo[i,j] for each test “

j”

performed on chip “

i”

, said test biasing factor being Θ

[i], said test result value being “

value[i,j]”

for each test “

j”

performed on chip “

i”

, said weight point for said test “

j”

being Y[i,j] for chip “

i”

, said means for calculating a weight point “

Y[i,j]”

for each test “

j”

performed on chip “

i”

, comprising;

means for calculating Y[i,j]=|(“

value[i,j]”

−

“

speclo[i,j”

)/“

speclo[i,j”

|−

Θ

[i] for condition of “

value[i,j]”

≦

“

speclo[i,j]”

;

or

means for calculating Y[i,j]=0 for condition of “

speclo[i,j]”

≦

“

value[i,j]”

≦

“

spechi[i,j]’

;

or

means for calculating Y[i,j]=|(“

value[i,j]”

−

“

spechi[i,j]”

)/“

spechi[i,j]”

|−

Θ

for condition of “

value[i,j]”

>

“

spechi[i,j]”

.

32. The system of claim 28, said means for dividing said chip class C[i] into at least one multiple chip class comprising means for sorting said at least one chip class in numerically incrementing values.

33. The system of claim 28, said chips comprising DRAM devices.

34. The system of claim 28, further extending this system to providing means for assigning a class designation to said wafer ID comprising:

means for determining a maximum value of said chip class C[i], creating a value of max C[i]; and

means for assigning said value of max C[i] to said wafer ID, creating a wafer class W[w].

35. The system of claim 34, further extending this system to providing means for assigning a class designation to a wafer lot having a lot ID, said lot ID comprising multiple said wafer ID, comprising:

summarizing said C[i] within a wafer ID for each value of “

i”

, creating a sum [i];

selecting a maximum value of sum[i], creating a max sum[i]; and

assigning said max sum[i] to said lot ID.

36. A system for sorting semiconductor devices in support of an Automatic Classification Shipping function, comprising:

means for testing said semiconductor devices by applying “

n”

tests to said devices thereby obtaining a test result value, said testing comprising assigning a high limit value and a low limit value to device test criteria, further comprising assigning a test biasing factor Θ

;

means for calculating a weight point Y for each test based on test results obtained;

means for adding all calculated weight points for a semiconductor device, creating a Summary of Weight Points for a semiconductor device;

means for assigning a class to said semiconductor device based on said Summary of Weight Points; and

sorting said classes assigned to said semiconductor devices Summary in numerical sequence.

37. The system of claim 36, said high limit value being “

spechi” and

said low limit value being “

speclo for each test “

j”

performed on chip “

i”

, said test biasing factor being Θ

[i], said test result value being “

value”

for each test “

j”

performed on chip “

i”

, said weight point being Y, said means for calculating a weight point comprising;

means for calculating Y=|(“

value”

−

“

speclo”

)/“

speclo”

|−

Θ

for condition of “

value”

≦

“

speclo”

;

or

means for calculating Y=0 for condition of “

speclo”

≦

“

value”

≦

“

spechi”

;

or

means for calculating Y=|(“

value]”

−

“

spechi”

)/“

spechi”

|−

Θ

for condition of “

value”

>

“

spechi”

.

38. The system of claim 36, said semiconductor devices comprising DRAM devices.

39. The system of claim 36, said system being applied to sorting semiconductor devices created over the surface of one wafer.

40. The system of claim 36, said system being applied to sorting semiconductor devices created over the surface of multiple wafers.

41. The system of claim 40, said system further being extended to providing means for assigning a wafer class to individual wafers having a wafer ID of said multiple wafers, said extension comprising providing means for identifying the class that is maximally assigned to semiconductor devices created over the surface of one wafer having a wafer ID and providing means for assigning this class to said wafer ID.

42. The system of claim 41, said system further being extended to providing means for assigning a lot class to individual lots having a lot ID comprising said multiple wafers, said extension comprising means for identifying the class that is maximally assigned to wafers pertaining to said lot ID and providing means for assigning this class to said lot ID.