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Shared peripheral architecture

  • US 20040088459A1
  • Filed: 10/30/2003
  • Published: 05/06/2004
  • Est. Priority Date: 09/13/2000
  • Status: Active Grant
First Claim
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1. An embedded computing system, comprising:

  • a plurality of processors;

    a bus coupling to a plurality of peripheral units;

    a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and

    a set of peripheral-share registers wherein each member of the set includes an entry associated with each of the plurality of peripheral units holding a state value indicating which of the plurality of processors currently owns the associated peripheral unit.

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