Shared peripheral architecture
First Claim
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1. An embedded computing system, comprising:
- a plurality of processors;
a bus coupling to a plurality of peripheral units;
a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and
a set of peripheral-share registers wherein each member of the set includes an entry associated with each of the plurality of peripheral units holding a state value indicating which of the plurality of processors currently owns the associated peripheral unit.
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Abstract
A disk drive controller including a plurality of processors and a plurality of shared peripheral units. A shared bus couples the peripheral units and the processors. A bi-directional multiplexor selectably couples each of the plurality of processors to the shared bus in response to an owner signal. A set of peripheral-share registers where a first member of the set includes an entry associated with each of the plurality of peripheral units and holds a state value indicating which of the plurality of processors currently owns the associated peripheral unit.
21 Citations
30 Claims
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1. An embedded computing system, comprising:
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a plurality of processors;
a bus coupling to a plurality of peripheral units;
a multiplexor for coupling each of the plurality of processors to the bus in response to an owner signal; and
a set of peripheral-share registers wherein each member of the set includes an entry associated with each of the plurality of peripheral units holding a state value indicating which of the plurality of processors currently owns the associated peripheral unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method for sharing a plurality of peripheral units in a controller having a plurality of processors comprising:
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generating a plurality of access requests using the plurality of processors;
storing a state value associated with each peripheral unit, the state value indicating which of the plurality of processors is a current owner of the associated peripheral; and
selectively coupling each peripheral unit to receive only access requests generated by a particular processor indicated by the state value associated with that peripheral unit. - View Dependent Claims (10, 11, 12)
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13. A multiprocessor controller, comprising:
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first and second processor cores;
a plurality of peripherals;
a bus coupling the processor cores to the peripherals; and
means for arbitrating between the processor cores for communication access to requested ones of the peripherals, whereby each of the peripherals is only used by one of the core processors at a particular time, wherein the arbitrating means comprises logic for determining which of the processor cores is an owner of a requested one of the peripherals. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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20. A multiprocessor computer system, comprising:
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a pair of processors;
an input/output bus connected to the processors;
a plurality of peripheral units connected to the input/output bus; and
a multiplexor for selectably coupling each of the processors to the shared input/output, wherein the multiplexor comprises an address multiplexor coupled to address outputs of each of the processors wherein the address multiplexor selectively couples one of the processor address outputs to a MUX address output; and
a data multiplexor coupled to data outputs of each of the processors, wherein the data multiplexor selectively couples one of the processor data outputs to a MUX data output. - View Dependent Claims (21, 22, 23, 24)
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25. A multiprocessor computing system, comprising:
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a pair of processors;
a plurality of peripheral units;
a bus coupling to each of the peripheral units; and
a multiplexor selectively coupling each of the plurality of processors to the bus in response to an owner signal, wherein the processors, the peripheral units, and the multiplexor comprise a single integrated circuit. - View Dependent Claims (26, 27, 28, 29, 30)
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Specification