Event delivery

• US 20040088460A1
• Filed: 10/31/2002
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Poisner, David I.
• Granted Patent: US 7,051,137 B2
• Time in Patent Office: Days
• US Class Current: 710/260
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

Claims

1. An apparatus comprising

a pin to transfer event signals associated with an event,

a bus interface to transfer bus messages,

a selection register to select a delivery mechanism for the event, and

an event handler to handle the event via a virtual wire message of the bus in response to the selection register selecting virtual wire message delivery for the event and to handle the event via an event signal of the pin in response to the selection register selecting pin delivery for the event.

2. The apparatus of claim 1 further comprising a capabilities register to indicate supported event delivery mechanisms.

3. The apparatus of claim 1 wherein the selection register comprises a lock field to enable locking of the selection register from further updates.

4. The apparatus of claim 1 wherein the event handler is to handle the event via an interrupt message of the bus in response to the selection register selecting interrupt message delivery for the event.

5. The apparatus of claim 1 wherein the event comprises a floating point error event.

6. The apparatus of claim 1 wherein the event comprises an ignore number error event.

7. The apparatus of claim 1 wherein the event comprises a thermal event error event.

8. The apparatus of claim 1 wherein the event comprises a power saving event.

9. The apparatus of claim 1 wherein the event handler is part of a processor and the event comprises a system control interrupt asserted by the event handler.

10. A method comprising

determining event delivery mechanisms that are commonly supported by the processor and chipset, and

selecting an event delivery mechanism for an event based upon the commonly supported event delivery mechanisms of the processor and the chipset.

11. The method of claim 10 further comprising

accessing a capabilities register of the processor to determine which event delivery mechanisms are supported by the processor, and

accessing a capabilities register of the chipset to determine which event delivery mechanisms are supported by the chipset.

12. The method of claim 11 further comprising

updating a selection register of the processor to select the event delivery mechanism for the event, and

updating a selection register of the chipset to select the event delivery mechanism for the event.

13. The method of claim 12 further comprising

locking the selection register of the processor to protect against further updates to the selection register of the processor, and

locking the selection register of the chipset to protect against further updates to the selection register of the chipset.

14. The method of claim 10 further comprising

selecting event delivery mechanisms for a plurality of events based upon the commonly supported event delivery mechanisms.

15. The method of claim 10 further comprising

delivering the event via an event signal associated with pins of the processor and the chipset in response to selecting pin delivery for the event,

delivering the event via an interrupt message in response to selecting interrupt message delivery for the event, and

delivering the event via a virtual wire message in response to selecting virtual wire message delivery for the event.

16. The method of claim 10 further comprising

delivering the event via an event signal associated with pins of the processor and the chipset in response to selecting pin delivery for the event, and

delivering the event via a virtual wire message in response to selecting virtual wire message delivery for the event.

17. The method of claim 10 further comprising

requesting the chipset to send a virtual wire message that provides status of the event in the chipset.

18. The method of claim 17 further comprising

requesting the processor to send a virtual wire message that provides status of the event in the processor.

19. The method of claim 10 further comprising

requesting the chipset to periodically send a virtual wire message that provides status of the event in the chipset.

20. The method of claim 19 further comprising

requesting the processor to periodically send a virtual wire message that provides status of the event in the processor.

21. A machine-readable medium comprising a plurality of instructions that in response to being executed by a computing device results in the computing device

determining event delivery mechanisms supported by a processor,

determining event delivery mechanisms supported by the chipset, and

selecting an event delivery mechanism for each of a plurality of events based upon the commonly supported event delivery mechanisms of the processor and the chipset.

22. The machine-readable medium of claim 21 wherein the plurality of instructions, in response to being executed by the computing device, further results in the computing device

accessing one or more capabilities registers of the processor to determine the event delivery mechanisms supported by the processor, and

accessing one or more capabilities registers of the chipset to determine the event delivery mechanisms supported by the chipset.

23. The machine-readable medium of claim 22 wherein the plurality of instructions, in response to being executed by the computing device, further results in the computing device

updating one or more selection registers of the processor to select the event delivery mechanisms for the plurality of events, and

updating one or more selection registers of the chipset to select the event delivery mechanisms for the plurality of events.

24. The machine-readable medium of claim 23 wherein the plurality of instructions, in response to being executed by the computing device, further results in the computing device

locking the one or more selection registers of the processor to protect against further updates to the one or more selection registers of the processor, and

locking the one or more selection registers of the chipset to protect against further updates to the one or more selection register of the chipset.

25. The machine-readable medium of claim 21 wherein the plurality of instructions, in response to being executed by the computing device, further results in the computing device

selecting between pin delivery and virtual wire message delivery for each of the plurality of events based upon the common delivery mechanisms of the processor and the chipset.

26. The machine-readable medium of claim 21 wherein the plurality of instructions, in response to being executed by the computing device, further results in the computing device

selecting among pin delivery, virtual wire message delivery, and interrupt message delivery for each of the plurality of events based upon the common deliver mechanisms of the processor and the chipset.

27. A system comprising

a processor comprising a bus interface to receive a virtual wire message and an event handler to decode the virtual wire message received via the bus interface,

a chipset comprising a bus interface to send the virtual wire message and an event handler to construct the virtual wire message to report status of a plurality of events, and

a bus to couple the bus interface of the processor to the bus interface of the chipset and to carry virtual wire messages therebetween.

28. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an INTR event associated with normal interrupts,

the processor lacks an INTR pin to receive an INTR event signal reporting status of the INTR event, and

the chipset lacks an INTR pin to send the INTR event signal.

29. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an NMI event associated with non-maskable interrupts,

the processor lacks an NMI pin to receive an NMI event signal reporting status of the NMI event, and

the chipset lacks an NMI pin to send an NMI event signal.

30. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an SMI event associated with system management interrupts,

the processor lacks an SMI pin to receive an SMI event signal reporting status of the SMI event, and

the chipset lacks an SMI pin to send an SMI event signal.

31. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an INIT event associated with processor initialization,

the processor lacks an INIT pin to receive an INIT event signal reporting status of the INIT event, and

the chipset lacks an INIT pin to send an INIT event signal.

32. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises a STPCLK event associated with a processor power reduced state,

the processor lacks an STPCLK pin to receive an STPCLK event signal reporting status of the STPCLK event, and

the chipset lacks an STPCLK pin to send an STPCLK event signal.

33. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an PROCHOT event associated with processor throttling,

the processor lacks an PROCHOT pin to receive an PROCHOT event signal reporting status of the PROCHOT event, and

the chipset lacks an PROCHOT pin to send an PROCHOT event signal.

34. The system of claim 27 wherein

the plurality of events of the virtual wire message comprises an A20M event associated with masking an A20M signal line of the bus,

the processor lacks an A20M pin to receive an A20M event signal reporting status of the A20M event, and

the chipset lacks an A20M pin to send an A20M event signal.

35. The system of claim 27 wherein the processor and chipset each comprise a plurality of event pins, the system further comprising

firmware that, in response to being executed by the processor, results in the processor for each event selecting between pin delivery and virtual wire message delivery.

36. The system of claim 27 wherein the chipset sends the processor the virtual wire message in response to a request.

37. The system of claim 27 wherein the chipset periodically sends the processor the virtual wire message regardless of an event status change.