Methods and systems for a memory section

• US 20040088477A1
• Filed: 10/31/2002
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: RPX Corporation
• Original Assignee: Ring Technology Enterprises of Texas LLC (IPNav)
• Inventors: Bullen, Melvin James, Lynch, William Thomas, Dodd, Steven Louis, Herbison, David James
• Granted Patent: US 7,707,351 B2
• Time in Patent Office: Days
• US Class Current: 711/109
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/067 Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers

Abstract

A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, and a section controller. In this system, a data request for the data may be received over a communications path by a section controller. The section controller determines the addresses in the memory devices storing the requested data, transfers these addresses to those memory devices storing the requested data, and transfers an identifier to the memory interface device. The memory device, in response, reads the data and transfers the data to its corresponding memory interface device. The memory interface device then adds to the data the identifier it received from the section controller and forwards the requested bits towards their destination, such that the data need not pass through the section controller.

Claims

1. A memory section, comprising

one or more memory devices for storing data locatable by one or more addresses, the memory devices capable of receiving control signals;

a memory section controller for receiving a request for data stored by the memory device, determining one or more addresses for the requested data, determining an identifier for use in forwarding the requested data, and transferring a control signal to the memory devices including the determined addresses to the memory device storing the requested data; and

a memory interface device for receiving from the memory device the requested data stored by the memory devices, receiving from the memory section controller the determined identifier for use in forwarding the requested data, and combining the requested data and the determined identifier, and forwarding the requesting data to a destination device.

2. The memory section of claim 1, wherein the identifier for use in forwarding the requested data is an address for a device to which the data are to be forwarded.

3. The memory section of claim 1, wherein the identifier for use in forwarding the requested data is an identifier for identifying the data that are to be forwarded.

4. The storage system of claim 1, wherein the memory devices include outputs, and wherein at least one of the memory interface devices includes:

at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein the shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the clock signal; and

wherein data from one or more of the output of a memory device is loaded into a corresponding shift register in the sets of shift registers and the loaded data is shifted from the shift register to a next one of the shift registers in the set according to the clock signal, such that the clock signal received by the shift register maintains its shift frequency during any loading of the data.

5. The storage system of claim 1, wherein the memory devices include outputs, and wherein at least one of the memory interface devices includes:

at least one set of shift registers interconnected in series, wherein at least one of the shift registers receives a clock signal having a shift frequency, and wherein the shift register is capable of shifting data loaded into the shift register to a next one of the shift registers in the set according to the clock signal; and

wherein data in the set of shifted register is loaded according to the clock signal from one or more shift registers in the set into one or more of the memory devices via an input corresponding to the shift register, such that the clock signal received by the shift register maintains its shift frequency during any loading of the data.

6. The memory section of claim 1, wherein the memory interface device further includes

at least one set of shift registers interconnected in series including:

at least one set of shift registers interconnected in series for writing data to the memory device,

and a at least one set of shift registers interconnected in series for reading data from the memory device; and

wherein data loaded into the sets of shift registers are shifted from one of the shift registers in the set to a next one of the shift registers in the set according to a clock signal.

7. The memory section of claim 1, wherein the determined addresses include a starting address and number of bits to transfer;

and

the memory section controller includes an internal memory in which the starting address and number of bits to transfer may be placed such that they are transferred to the memory device in order to cause the memory device to transfer the data at the locations specified by the starting address and number of bits to transfer.

8. The memory section of claim 1, further comprising

a switch for receiving the requested data from the memory interface device corresponding to the memory device and transferring the data to one of the one or more communications paths;

wherein the switch receives a control signal from the memory section controller that indicates which of the one or more communications paths to use to send the requested data.

9. The memory section of claim 1, wherein the memory section sends the requested data to a switch that uses the identifier to forward the requested data to the destination device.

10. The memory section of claim 1, wherein the memory section controller is further capable of providing test data to the memory devices and checking test data received from the memory devices and determining a fault based on the checking of the test data.

11. The storage system of claim 1, wherein the storage locations of the memory devices are partitioned into data blocks that are identifiable by a data block identifier, and wherein a data request received by the memory section includes a data block identifier that is forwarded to the memory section controller;

and wherein the memory section controller determines one or more addresses based on the data block identifier and provides the determined addresses to the one or more memory devices.

12. The memory section of claim 1, wherein the memory section further includes

a temporary storage device for storing data to be written to a memory device;

and

a temporary storage interface device for storing data in and retrieving data from the temporary storage device;

wherein data to be stored in the memory section is forwarded to the temporary storage interface device, and wherein the temporary storage interface stores the data in the temporary storage device if a memory device to which the data is to be written is busy, and wherein the temporary storage interface device retrieves the data from the temporary storage device when the memory device is no longer busy and forwards the data to the memory device such that the memory device stores the data.

13. The memory section of claim 1, wherein the memory section further includes at least one communications channel interface for receiving data to be stored by the memory section and transferring the data to be stored to one or more of the memory devices, and wherein the communications channel interface is further capable of receiving data read from the memory devices and transferring the data read from the memory devices from the memory section via one or more communications channels, and wherein the communications channel interface is further capable of receiving data requests and forwarding the data requests to the memory section controller.

15. The storage system of claim 13, wherein the identifier for use in forwarding the requested data is an address for a device to which the data are to be forwarded.

16. The storage system of claim 13, wherein the identifier for use in forwarding the requested data is an identifier for identifying the data that are to be forwarded.

17. The storage system of claim 13, further comprising:

one or more switches connected to one or more of the memory sections and one or more communications channels, and

a management system for determining an algorithm for use by the switch in connecting the one or more memory sections and the one or more communications channels and providing the determined algorithm to the switch.

18. The storage system of claim 13, further comprising:

one or more switches; and

a management system capable of instructing the storage system to store a back-up of data stored by one or more of the memory sections into a non-volatile storage device connected to at least one of the switches, receiving a fault message from a memory section, and instructing the storage system to load the back-up of faulty memory section'"'"'s data from the non-volatile storage device into a functioning memory section.

19. The storage system of claim 13, further comprising:

one or more switches; and

wherein the storage locations of the memory devices are partitioned into data blocks that are identifiable by a data block identifier, and wherein a data request received by the storage system includes a data block identifier; and

wherein a switch receiving the data request directs the data request to a memory section storing the data block identified by the data block identifier; and

wherein the memory section reads data stored in the storage locations of the memory devices identified by the data block identifier and forwards the read data to destination device via the switch.

14. A storage system comprising:

one or more memory sections including

one or more memory devices for storing data locatable by one or more addresses, the memory devices capable of receiving control signals;

a memory section controller for receiving a request for data stored by the memory device, determining one or more addresses for the requested data, determining an identifier for use in forwarding the requested data, and transferring a control signal including the determined addresses to the memory device storing the requested data; and

a memory interface device for receiving from the memory device the requested data stored by the memory devices, receiving from the memory section controller the determined identifier, and combining the requested data and the determined identifier, and forwarding the requesting data to a destination device.

20. A method for use in a storage system, comprising:

storing data in storage locations in a memory device, the storage locations identifiable by addresses;

receiving by a memory section controller a data request for data stored by the memory device;

the memory section controller determining one or more addresses for the requested data;

the memory section controller determining an identifier for use in forwarding the requested data;

the memory section controller transferring a control signal to the memory device the control signal including the determined addresses;

the memory section controller transferring the determined identifier to a memory interface device;

the memory interface device receiving from the memory device the requested data;

the memory interface device combining the identifier and the requested data;

the memory interface device forwarding the requested data to a destination device.

21. The method of claim 20, further comprising:

shifting data in one or more shift registers in a set of shift registers interconnected in series from the shift register to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency, wherein the shift registers are included in the memory interface device;

loading data from the memory device into a corresponding shift register in the set; and

shifting the data loaded into one or more of the shift registers to a next one of the shift registers in the set according to the clock signal, wherein the clock signal maintains its shift frequency during the loading of the data from the memory devices into the shift registers.

22. The method of claim 20, further comprising:

shifting data in one or more shift registers in a set of shift registers interconnected in series from the shift registers to a next one of the shift registers in the set on the basis of a clock signal having a shift frequency, the shift registers included in the memory interface device;

loading data from one or more of the shift registers to the memory device; and

shifting the data loaded from the one or more shift registers to a next one of the shift registers in the set according to the clock signal after the data is loaded into the memory device, wherein the clock signal maintains its frequency during the loading of the data.

23. The method of claim 20, wherein the memory interface device further includes at least one set of shift registers interconnected in series for writing data to the memory device, and at least one set of shift registers interconnected in series for reading data from the memory device, the method further comprising:

shifting data loaded into the sets of shift registers from one of the shift registers in the set to a next one of the shift registers in the set according to a clock signal.

24. The method of claim 20, wherein the determined addresses include a starting address and number of bits to transfer, further comprising:

placing the starting address and number of bits to transfer in an internal memory of the memory section controller;

transferring the starting address and number of bits to transfer from the memory section controller to the memory device; and

the memory device transferring the data at the locations specified by the starting address and number of bits to transfer in response to receiving the starting address and number of bits to transfer.

25. The method of claim 20, further comprising

a switch receiving the requested data from the memory interface device corresponding to the memory device;

the switch transferring the data to one or more communications paths; and

the switch receiving a control signal from the memory section controller that indicates which of the one or more communications paths to use to send the requested data.

26. The method of claim 20, further comprising:

the memory section sending the requested data to a switch that uses the identifier to forward the requested data to the destination device.

27. The method of claim 20, further comprising:

the memory section controller providing test data to the memory devices;

the memory the section controller receiving the test data from the memory interface devices;

the memory section controller checking the received data; and

the memory section controller determining a fault based on the checking of the test data.

28. The method of claim 20, wherein the storage locations of the memory devices are partitioned into data blocks that are identifiable by a data block identifier, and wherein a data request received by the memory section includes a data block identifier, further comprising

forwarding the data request to the memory section controller;

the memory section controller determining one or more addresses based on the data block identifier; and

the memory section controller providing the determined addresses to the one or more memory devices.

29. The method of claim 20, further comprising:

receiving data to be stored in the memory device;

forwarding the data to a temporary storage interface device;

the temporary storage device storing data to be stored in a temporary storage device if the memory device to which the data is to be written is busy;

the temporary storage interface device retrieving the data from the temporary storage device when the memory device to which the data is to be stored is no longer busy; and

the memory device storing the data.

30. A storage system, comprising:

means for storing data in storage locations identifiable by addresses;

means for controlling, including;

means for receiving a data request for data stored by the memory device;

means for determining one or more addresses for the requested data;

means for determining an identifier for use in forwarding the requested data;

means for transferring a control signal to the means for storing, the control signal including the determined addresses; and

means for accessing data in the means for storing, the means for accessing, including;

means for receiving from the means for storing the requested data;

means for receiving from the means for controlling the determined identifier;

means for combining the identifier and the requested data; and

means for forwarding the requested data to a destination device.