Storage controller

• US 20040088484A1
• Filed: 07/09/2003
• Published: 05/06/2004
• Est. Priority Date: 09/12/1997
• Status: Active Grant

• Current Assignee: Akira Yamamoto, Katsunori Nakamura, Shigeru Kishiro
• Original Assignee: Akira Yamamoto, Katsunori Nakamura, Shigeru Kishiro
• Inventors: Yamamoto, Akira, Kishiro, Shigeru, Nakamura, Katsunori
• Granted Patent: US 7,216,208 B2
• Time in Patent Office: Days
• US Class Current: 711/114
• CPC Class Codes: G06F 11/2064 while ensuring consistency
• CPC Class Codes: G06F 11/2071 using a plurality of controllers
• CPC Class Codes: G06F 11/2074 Asynchronous techniques
• CPC Class Codes: G06F 2201/82 Solving problems relating to consistency ensuring consistency in mirrored systems G06F11/2064

Abstract

A primary controller operates to transmit write data and a write time to a secondary controller in the earlier sequence of the write times after reporting a completion of a request for write to a processing unit. The secondary controller stores the write data and the write time transmitted from the primary controller in the cache memory. At a time, the secondary controller stores the write data in a disk unit in the earlier sequence of the write time. These operations make it possible to guarantee all the write data on or before the reference time.

Claims

1. A computer system comprising:

a processing unit;

a first controller connected to said processing unit and having a first cache memory;

a first disk unit connected to said first controller;

a second controller connected to said first controller and having a second cache memory;

a second disk connected to said second controller; and

wherein

said processing unit issues a request for write containing write data and a write time to said first controller,

said first controller (a) stores said write data in said first cache memory, (b) reports completion of said request for write to said processing unit, (c) stores said write data stored in said first cache memory in said first disk unit, and (d) transmits said write data and said write time stored in said first cache memory to said second controller in the sequence of said write time, wherein said steps (c) and (d) are executed in parallel, and

said second controller (e) stores said write data and write time transmitted from said first controller to said second cache memory and (f) stores said write data stored in said second cache memory to said second disk unit in the sequence of said write time.

2. The computer system according to claim 1, wherein after said step (e) is executed, said second controller transmits a report on completion to said first controller.

3. The computer system according to claim 1, wherein said first and second cache memories are non-volatile.

4. The computer system according to claim 1, further comprising:

another processing unit; and

wherein both of said processing units have common clocks to each other.

5. The computer system, comprising:

a processing unit;

a first controller connected to said processing unit and having a first cache memory;

a first disk unit connected to said first controller;

a second controller connected to said first controller and having a second cache memory;

a second disk unit connected to said second controller; and

wherein

said processing unit issues a request for write containing write data and a write time to said first controller,

said first controller (a) stores said write data in said first cache memory, (b) reports completion of said request for write to said processing unit, (c) stores said write data stored in said first cache memory to said first disk unit, (d) transmits plural pairs of said write data and said write time and a destageable time stored in said first cache memory to said second controller in the earlier sequence of said write times, wherein said steps (c) and (d) are executed in parallel, and

said second controller (e) stores said write data and said write time transmitted from said first controller in said second cache memory, and (f) stores in said second disk unit said write data corresponding to said earlier write time than said destageable time and stored in said second cache memory.

6. The computer system according to claim 5, wherein after said step (e) is executed, said second controller transmits a report on the completion to said first controller.

7. The computer system according to claim 5, wherein said first and second cache memories are non-volatile.

8. The computer system according to claim 5, further comprising:

another processing unit; and

wherein both of said processing units have common clocks.