Receiver tracking mechanism for an I/O circuit

• US 20040088594A1
• Filed: 10/31/2002
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dunning, David S., Drottar, Ken, Abhayagunawardhana, Chamath, Dabral, Sanjay, Canagasaby, Karthisha S.
• Application Number:
  US10/284,245
• Publication Number:
  US 20040088594A1
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A receiver circuit is provided with a front amplifier to receive data from an I/O link driven by a remote clock signal; an interpolator to generate a local clock signal to track the remote clock signal encoded in the data; and a tracking mechanism to extract phase information about the remote clock signal from the data and to dynamically adjust the phase of the local clock signal that tracks the remote clock signal in accordance with extracted phase information for subsequent data processing functions, wherein the tracking mechanism is configured to predict the direction of a phase drift, and force the interpolator to move against the phase drift so as to reduce lock time.

Claims

1. A receiver circuit, comprising:

a front amplifier to receive data from an I/O link driven by a remote clock signal;

an interpolator to generate a local clock signal to track the remote clock signal encoded in the data; and

a tracking mechanism to extract phase information about the remote clock signal from the data and to dynamically adjust the phase of the local clock signal that tracks the remote clock signal in accordance with extracted phase information for subsequent data processing functions,

wherein the tracking mechanism is configured to predict a direction of a phase drift, and force the interpolator to move against the phase drift so as to reduce lock time.

2. The receiver circuit as claimed in claim 1, wherein the phase drift is measured between incoming data phase and the remote clock signal.

3. The receiver circuit as claimed in claim 1, wherein the tracking mechanism comprises:

a vote generator to vote whether to move up/down the local clock signal based on the accumulation and analysis of both data and edge samples;

a loop filter to provide appropriate filter amplification of the up/down votes from the vote generator;

a drift direction predictor to predict the direction of the phase drift; and

an interpolator control unit to control operation of the interpolator, including drift compensation, based on up/down controls from the loop filter.

4. The receiver circuit as claimed in claim 3, wherein the drift direction predictor includes a direction predictor logic arranged to predict the direction of the phase drift, and a drift predictor logic arranged to predict the drift compensation necessary to ensure the interpolation movement “

against the drift”

.

5. The receiver circuit as claimed in claim 3, wherein the interpolator control unit is configured to delay/advance phases of the local clock signal until a lock condition is established, in accordance with the up/down votes from the vote generator.

6. The receiver circuit as claimed in claim 1, wherein the tracking mechanism comprises:

a phase comparison circuit to compare phases of the remote clock signal and the local clock signal;

a loop filter to provide appropriate filter amplification to up/down controls from the phase comparison circuit;

a drift direction predictor to predict the direction of the phase drift; and

an interpolator control unit to control the operation of the interpolator, including drift compensation, based on the up/down controls from the loop filter.

7. The receiver circuit as claimed in claim 6, wherein the drift direction predictor includes a direction predictor logic arranged to predict the direction of the phase drift, and a drift predictor logic arranged to predict the drift compensation necessary to ensure the interpolation movement “

against the drift”

.

8. The receiver circuit as claimed in claim 7, wherein the direction predictor logic comprises:

D flip-flops arranged to receive the up/down controls from the loop filter and produce logic outputs that indicate the drift direction; and

an OR gate arranged to logically combine the outputs from the D flip-flops and provide a feedback to control the D flip-flops.

9. The receiver circuit as claimed in claim 7, wherein the drift predictor logic comprises:

counters arranged to count the remote clock signal and the local clock signal; and

a comparator arranged to compare clock counts from the counters, determine the drift direction based on a difference in clock counts and provide the drift compensation to ensure that the interpolator movement is “

against the drift”

.

10. The receiver circuit as claimed in claim 1, wherein the interpolator comprises:

a plurality of differential transistor pairs, each pair of differential transistors having sources and drains commonly coupled, and gate electrodes coupled to receive a phase pair of a reference clock signal, via input terminals; and

a plurality of tail current sources coupled to the commonly coupled sources of each pair of differential transistors, to interpolate between the phase pair of the reference clock signal; and

one or more active loads commonly coupled to the drains of the differential transistor pairs, via an output terminal;

wherein the tail current sources coupled to the commonly coupled sources of each pair of differential transistors utilize 2;

1 current weighting at outer tail current sources relative to inner tail current sources to apportion and distribute the current among phases of the reference clock signal that are being interpolated while maintaining the total current drawn to improve linearity of the interpolator.

11. The receiver circuit as claimed in claim 10, wherein the interpolator further comprises CMOS capacitors coupled to the output terminal to provide a controllable amount of capacitance at the output terminal to improve the linearity of the interpolator.

12. The receiver circuit as claimed in claim 10, wherein the current tail sources are current source transistors implemented to weight current to its tails and distribute the current among the phases of the reference clock signal that are being interpolated while maintaining the total current drawn.

13. The receiver circuit as claimed in claim 10, wherein each of the differential transistor pairs comprises one selected from a group consisting of N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, and bipolar junction transistors (BJTs).

14. The receiver circuit as claimed in claim 10, wherein at least one of the one or more active loads comprises one selected from a group consisting of resistors, diode-connected N-type MOSFETs, and P-type MOSFETs.

15. The receiver circuit as claimed in claim 1, further comprising:

a synchronization and alignment unit (SAU) arranged between the front amplifier and the tracking mechanism, to align and synchronize data and edge samples and provide extra settling time to sensitive edge samples for meta-stability.

16. The receiver circuit as claimed in claim 15, wherein the synchronization and alignment unit (SAU) comprises:

an alignment unit arranged to align the edge and data samples and provide extra settling time to the sensitive edge samples for meta-stability; and

a synchronization buffer arranged to synchronize and buffer aligned samples to be forwarded to the tracking mechanism to extract the phase error obtained between the local sampling clock and data transitions for dynamic phase tracking and adjustment.

17. The receiver circuit as claimed in claim 16, wherein the alignment unit comprises:

a first D flip-flop arranged to receive edge samples by a first phase of the reference clock signal and to produce a logic output indicating delayed edge samples;

a second D flip-flop arranged to receive data samples by a second phase of the reference clock signal, via a first buffer, and to produce a logic output indicating delayed data samples;

a third D flip-flop arranged to receive edge samples by a third phase of the reference clock signal and to produce a logic output indicating delayed edge samples;

a fourth D flip-flop arranged to receive data samples by a fourth phase of the reference clock signal, via a second buffer, and to produce a logic output indicating delayed data samples;

a fifth D flip-flop arranged to receive delayed edge samples from the first D flip-flop, via a third buffer, and to produce aligned edge samples;

a sixth D flip-flop arranged to receive delayed data samples from the second D flip-flop, via a fourth buffer, and to produce aligned data samples;

a seventh D flip-flop arranged to receive edge samples from the third D flip-flop and to produce aligned edge samples; and

an eighth D flip-flop arranged to receive delayed data samples from the fourth D flip-flop and to produce aligned data samples.

18. The receiver circuit as claimed in claim 3, wherein the vote generator is implemented as a programmable logic array (PLA) or a look-up table arranged to receive edge and data samples and generate, in accordance with the accumulation and analysis of both edge and data samples relative to the local clock signal, the up/down vote used to advance/delay the phases of the local clock signal until a lock condition is established.

19. The receiver circuit as claimed in claim 3, wherein the loop filter comprises:

a plurality of loop filter stages arranged in a cascade to determine if the difference between the up/down vote is equal greater than a desired threshold; and

a multiplexor arranged to select outputs from the cascading loop filter stages based on a filter selection signal.

20. A phase tracking interpolator, comprising:

a plurality of differential transistor pairs, each pair of differential transistors having sources and drains commonly coupled, and gate electrodes coupled to receive a phase pair of a reference clock signal, via input terminals; and

a plurality of tail current sources coupled to the commonly coupled sources of each pair of differential transistors, to interpolate between the phase pair of the reference clock signal; and

one or more active loads commonly coupled to the drains of the differential transistor pairs, via an output terminal;

wherein the tail current sources coupled to the commonly coupled sources of each pair of differential transistors utilize 2;

1 current weighting at outer tail current sources relative to inner tail current sources to apportion and distribute the current among phases of the reference clock signal that are being interpolated while maintaining the total current drawn to improve linearity of the interpolator.

21. The phase tracking interpolator as claimed in claim 20, further comprising CMOS capacitors coupled to the output terminal to provide a controllable amount of capacitance at the output terminal to improve the linearity of the interpolator.

22. The phase tracking interpolator as claimed in claim 20, wherein the current tail sources are current source transistors implemented to weight current to its tails and distribute the current among the phases of the reference clock signal that are being interpolated while maintaining the total current drawn.

23. The phase tracking interpolator as claimed in claim 20, wherein each of the differential transistor pairs comprises one selected from a group consisting of N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, and bipolar junction transistors (BJTs).

24. The phase tracking interpolator as claimed in claim 20, wherein at least one of the one or more active loads comprises one selected from a group consisting of resistors, diode-connected N-type MOSFETs, and P-type MOSFETs.

25. A phase tracking interpolator comprising;

at least one pair of differential transistors having sources and drains commonly coupled, and gate electrodes coupled to receive a phase pair of a reference clock signal; and

tail current sources coupled to the commonly coupled sources of the differential transistor pair, to interpolate between the phase pair of the reference clock signal; and

at least one active load coupled to the commonly coupled drains of the differential transistor pair;

wherein the tail current sources coupled to the commonly coupled sources of each pair of differential transistors utilize a predetermined current weighting ratio at outer tail current sources relative to inner tail current sources to apportion and distribute the current among phases of the reference clock signal that are being interpolated while maintaining the total current drawn to improve linearity of the interpolator.

26. The phase tracking interpolator as claimed in claim 25, further comprising CMOS capacitors coupled to the commonly coupled drains of the differential transistor pair to provide a controllable amount of capacitance at an output terminal to improve the linearity of the interpolator.

27. The phase tracking interpolator as claimed in claim 25, wherein the current tail sources are current source transistors implemented to weight current to its tails and distribute the current among the phases of the reference clock signal that are being interpolated while maintaining the total current drawn.

28. The phase tracking interpolator as claimed in claim 25, wherein the differential transistor pair comprises one selected from a group consisting of N-type metal oxide semiconductor field effect transistors (MOSFETs), P-type MOSFETs, and bipolar junction transistors (BJTs).

29. The phase tracking interpolator as claimed in claim 25, wherein the active load comprises one selected from a group consisting of resistors, diode-connected N-type MOSFETs, and P-type MOSFETs.

30. A receiver circuit comprising:

a front amplifier to receive data from an I/O link driven by a remote clock signal;

an interpolator to generate a local clock signal to track the remote clock signal encoded in the data;

an alignment unit to align data and edge samples and provide extra settling time to sensitive edge samples for meta-stability; and

a tracking mechanism to extract phase information about the remote clock signal from aligned data and edge samples, and to dynamically adjust the phase of the local clock signal that tracks the remote clock signal in accordance with extracted phase information for subsequent data processing functions.

31. The receiver circuit as claimed in claim 30, wherein the alignment unit comprises:

a first D flip-flop arranged to receive edge samples by a first phase of the reference clock signal and to produce a logic output indicating delayed edge samples;

a second D flip-flop arranged to receive data samples by a second phase of the reference clock signal, via a first buffer, and to produce a logic output indicating delayed data samples;

a third D flip-flop arranged to receive edge samples by a third phase of the reference clock signal and to produce a logic output indicating delayed edge samples;

a fourth D flip-flop arranged to receive data samples by a fourth phase of the reference clock signal, via a second buffer, and to produce a logic output indicating delayed data samples;

a fifth D flip-flop arranged to receive delayed edge samples from the first D flip-flop, via a third buffer, and to produce aligned edge samples;

a sixth D flip-flop arranged to receive delayed data samples from the second D flip-flop, via a fourth buffer, and to produce aligned data samples;

a seventh D flip-flop arranged to receive edge samples from the third D flip-flop and to produce aligned edge samples; and

an eighth D flip-flop arranged to receive delayed data samples from the fourth D flip-flop and to produce aligned data samples.

32. The receiver circuit as claimed in claim 30, wherein the tracking mechanism is configured to predict a direction of a phase drift, and force the interpolator to move against the phase drift so as to reduce lock time, the phase drift being measured between incoming data phase and the remote clock signal.

33. The receiver circuit as claimed in claim 30, wherein the tracking mechanism comprises:

a vote generator to vote whether to move up/down the local clock signal based on the accumulation and analysis of both data and edge samples;

a loop filter to provide appropriate filter amplification of the up/down votes from the vote generator;

a drift direction predictor to predict the direction of the phase drift; and

an interpolator control unit to control operation of the interpolator, including drift compensation, based on up/down controls from the loop filter.

34. The receiver circuit as claimed in claim 33, wherein the drift direction predictor includes a direction predictor logic arranged to predict the direction of the phase drift, and a drift predictor logic arranged to predict the drift compensation necessary to ensure the interpolation movement “

against the drift”

.

35. The receiver circuit as claimed in claim 34, wherein the direction predictor logic comprises:

D flip-flops arranged to receive the up/down controls from the loop filter and produce logic outputs that indicate the drift direction; and

an OR gate arranged to logically combine the outputs from the D flip-flops and provide a feedback to control the D flip-flops.

36. The receiver circuit as claimed in claim 34, wherein the drift predictor logic comprises:

counters arranged to count the remote clock signal and the local clock signal; and

a comparator arranged to compare clock counts from the counters, determine the drift direction based on a difference in clock counts and provide the drift compensation to ensure that the interpolator movement is “

against the drift”

.

37. The receiver circuit as claimed in claim 30, wherein the interpolator comprises:

at least one pair of differential transistors having sources and drains commonly coupled, and gate electrodes coupled to receive a phase pair of a reference clock signal; and

tail current sources coupled to the commonly coupled sources of the differential transistor pair, to interpolate between the phase pair of the reference clock signal; and

at least one active load coupled to the commonly coupled drains of the differential transistor pair;

wherein the tail current sources coupled to the commonly coupled sources of each pair of differential transistors utilize a predetermined current weighting ratio at outer tail current sources relative to inner tail current sources to apportion and distribute the current among phases of the reference clock signal that are being interpolated while maintaining the total current drawn to improve linearity of the interpolator.

38. The receiver circuit as claimed in claim 37, further comprising CMOS capacitors coupled to the commonly coupled drains of the differential transistor pair to provide a controllable amount of capacitance at an output terminal to improve the linearity of the interpolator.

39. The receiver circuit as claimed in claim 37, wherein the current tail sources are current source transistors implemented to weight current to its tails and distribute the current among the phases of the reference clock signal that are being interpolated while maintaining the total current drawn.

40. The receiver circuit as claimed in claim 33, wherein the vote generator is implemented as a programmable logic array (PLA) or a look-up table arranged to receive the edge and data samples and generate, in accordance with the accumulation and analysis of both edge and data samples relative to the local clock signal, the up/down vote used to advance/delay the phases of the local clock signal until a lock condition is established.