Redundant clock synthesizer

• US 20040088597A1
• Filed: 11/06/2002
• Published: 05/06/2004
• Est. Priority Date: 11/06/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Wu, Chung-Hsiao R.
• Granted Patent: US 7,043,655 B2
• Time in Patent Office: Days
• US Class Current: 713/500
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 11/1604 where the fault affects the clock signals of a processing unit and the redundancy is at or within the level of clock signal generation hardware
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Abstract

A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master, generating a system clock signal, while the second clock board acts as a slave. The first clock board may monitor a phase difference between a first crystal clock signal and a feedback clock signal. If the phase difference exceeds a limit, the first crystal clock signal may be inhibited, preventing the first clock board from generating the system clock signal. The second clock board may monitor the system clock board in reference to a feedback clock signal. If the second clock board detects a predetermined number of consecutive missing clock edges, it may enable a second crystal clock signal, which may be used to generate a system clock signal.

Claims

1. A computer system comprising:

a side plane board;

a first clock board coupled to the side plane board, the first clock board including a first crystal, a first buffer, and a first clock synthesizer circuit coupled to receive a first crystal clock signal from the first crystal and provide a first system clock signal to the first buffer; and

a second clock board coupled to the side plane board, the first clock board including a second crystal, a second buffer, and a second clock synthesizer circuit coupled to receive a second crystal clock signal from the second crystal and provide a second system clock signal to the second buffer;

wherein the first clock board is configured to operate as a master and the second clock board is configured to operate as a slave, wherein the first clock synthesizer is configured to determine a phase relationship between the first crystal clock signal and a first feedback clock signal, and wherein the first clock synthesizer is configured to inhibit the first crystal clock signal if the phase relationship exceeds a predetermined limit; and

wherein the second clock board, responsive to detecting the inhibiting of the first crystal clock signal, is configured to act as a master by enabling the second crystal clock signal.

2. The computer system as recited in claim 1, wherein the second clock board, when operating as a slave, is configured to compare the system clock signal received from the first clock board to a second feedback clock signal, and wherein the second clock board is configured to enable the second crystal clock signal responsive to detecting a plurality of consecutive missing clock edges from the system clock signal.

3. The computer system as recited in claim 2, wherein the second clock board is configured to enable the second crystal clock signal responsive to detecting 3 consecutive missing clock edges.

4. The computer system as recited in claim 2, wherein the missing clock edges include rising clock edges and falling clock edges.

5. The computer system as recited in claim 1, wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including:

a detect/compare circuit, the detect/compare circuit configured to receive a reference clock signal, a feedback clock signal, and a crystal clock signal, wherein the reference clock signal is the system clock signal;

a first multiplexer coupled to receive the crystal clock signal and the reference clock signal;

a second multiplexer coupled to receive the feedback clock signal and a test clock signal;

first and second clock divider circuits each coupled to receive a first output signal from the first and second multiplexers, respectively;

a programmable frequency circuit, wherein the programmable frequency circuit is coupled to provide dividing integers to the first and second clock divider circuits;

a phase locked loop circuit coupled to receive second and third output signals from each of the first and second clock divider circuits;

third and fourth clock divider circuits coupled to receive a fourth output signals, wherein the third clock divider circuit is configured to output the system clock signal and the fourth clock divider circuit is configured to output a test clock signal.

6. The computer system as recited in claim 5, wherein the programmable frequency circuit is coupled to receive programming information via a serial bus.

7. The computer system as recited in claim 5, wherein clock synthesizer chip is configured to allow the crystal clock signal to propagate through the first multiplexer when the clock synthesizer chip is a master and allow the reference clock signal to propagate through the first multiplexer when the clock synthesizer chip is a slave.

8. The computer system as recited in claim 7, wherein the detect/compare circuit is coupled to provide a select signal to the first multiplexer, wherein the select signal causes the crystal clock signal to be selected when the clock synthesizer is a master and the reference clock signal when the clock synthesizer is a slave.

9. The computer system as recited in claim 5, wherein each of the first and second clock boards includes a buffer, wherein the buffer is coupled to receive the system clock signal from the third clock divider circuit and the feedback clock signal.

10. The computer system as recited in claim 9, wherein the buffer is further configured to distribute the system clock signal to the computer system and provide the feedback clock signal to the input of the second multiplexer of the clock synthesizer chip, wherein the buffer and the clock synthesizer chip are mounted upon the same clock board.

11. The computer system as recited in claim 5, wherein the detect/compare circuit is coupled to receive a master/slave select input and a manual/auto select input.

12. The computer system as recited in claim 5, wherein the clock synthesizer is coupled to receive a test select signal, wherein the second multiplexer is configured to allow the feedback clock signal to propagate when the test select signal is de-asserted and further configured to allow the test clock signal to propagate when the test select signal is asserted.

13. A method comprising:

a first clock board monitoring a phase difference between a first crystal clock signal and a first feedback clock signal, wherein the first clock board is acting as a master, and wherein the first crystal clock signal is used to generate a system clock signal;

a second clock board receiving the system clock signal and monitoring the system clock signal in reference to a second feedback clock signal, wherein the second clock board is acting as a slave;

the first clock board detecting the phase difference exceeding a predetermined limit and inhibiting the first crystal clock signal;

the second clock board detecting a plurality of consecutive missing clock edges of the system clock signal;

the second clock board enabling a second crystal clock signal responsive to said detecting a plurality of missing edges, wherein the second crystal clock signal, upon enabling, is used to generate a system clock signal, and wherein the second clock board acts as a master when the second crystal clock signal is enabled.

14. The method as recited in claim 13, wherein the second clock board is configured to enable the second crystal clock signal responsive to detecting 3 consecutive missing clock edges.

15. The method as recited in claim 13, wherein the missing clock edges include rising clock edges and falling clock edges.

16. The method as recited in claim 13, wherein each of the first and second clock synthesizer circuits are implemented on a clock synthesizer chip, the clock synthesizer chip including:

a detect/compare circuit, the detect/compare circuit configured to receive a reference clock signal, a feedback clock signal, and a crystal clock signal, wherein the reference clock signal is the system clock signal;

a first multiplexer coupled to receive the crystal clock signal and the reference clock signal;

a second multiplexer coupled to receive the feedback clock signal and a test clock signal;

first and second clock divider circuits each coupled to receive a first output signal from the first and second multiplexers, respectively;

a programmable frequency circuit, wherein the programmable frequency circuit is coupled to provide dividing integers to the first and second clock divider circuits;

a phase locked loop circuit coupled to receive second and third output signals from each of the first and second clock divider circuits;

third and fourth clock divider circuits coupled to receive a fourth output signals, wherein the third clock divider circuit is configured to output the system clock signal and the fourth clock divider circuit is configured to output a test clock signal.

17. The method as recited in claim 16, wherein the programmable frequency circuit is coupled to receive programming information via a serial bus.

18. The method as recited in claim 16, wherein clock synthesizer chip is configured to allow the crystal clock signal to propagate through the first multiplexer when the clock synthesizer chip is a master and allow the reference clock signal to propagate through the first multiplexer when the clock synthesizer chip is a slave.

19. The method as recited in claim 18, wherein the detect/compare circuit is coupled to provide a select signal to the first multiplexer, wherein the select signal causes the crystal clock signal to be selected when the clock synthesizer is a master and the reference clock signal when the clock synthesizer is a slave.

20. The method as recited in claim 16, wherein each of the first and second clock boards includes a buffer, wherein the buffer is coupled to receive the system clock signal from the third clock divider circuit and the feedback clock signal.

21. The method as recited in claim 20, wherein the buffer is further configured to distribute the system clock signal to the computer system and provide the feedback clock signal to the input of the second multiplexer of the clock synthesizer chip, wherein the buffer and the clock synthesizer chip are mounted upon the same clock board.

22. The method as recited in claim 16, wherein the detect/compare circuit is coupled to receive a master/slave select input and a manual/auto select input.

23. The method as recited in claim 16, wherein the clock synthesizer is coupled to receive a test select signal, wherein the second multiplexer is configured to allow the feedback clock signal to propagate when the test select signal is de-asserted and further configured to allow the test clock signal to propagate when the test select signal is asserted.