Placement processing for programmable logic devices

• US 20040088663A1
• Filed: 11/05/2002
• Published: 05/06/2004
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Lattice Semiconductor Corporation
• Inventors: Shen, Yinan, Liu, Liren, Wu, Qinghong
• Granted Patent: US 6,813,754 B2
• Time in Patent Office: Days
• US Class Current: 716/6
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A method for placing configurable logic blocks (CLBs) in a PLD, such as an FPGA. In one embodiment, after packing gates/clusters into blocks and then assigning those blocks to CLBs to generate an initial placement, the packing and/or placement of CLBs is changed prior to performing CLB routing. For each node of the most critical of the K most critical paths in the initial placement, moving the node to a different CLB is considered in order to reduce the criticality of that path. A move is applied if certain acceptability conditions are met. After the most critical path is improved, the criticality of the K paths is updated, and the procedure is repeated for the new most critical of the K updated paths. The method, which can be automated to reduce human intervention in the design process, improves circuit performance, e.g., by enabling higher circuit operation frequencies.

Claims

1. A method of mapping a plurality of circuit elements onto a plurality of configurable logic blocks (CLBs) in a programmable logic device (PLD), comprising:

generating a mapping of the circuit elements to the CLBs in the PLD;

selecting a critical path in the PLD corresponding to the mapping; and

for at least one node of the critical path, changing node assignment from a current location to a different location based on change of circuit performance corresponding to the change in node assignment.

2. The invention of claim 1, wherein the method is implemented using a computer.

3. The invention of claim 2, wherein changing node assignment is performed automatically by the computer.

4. The invention of claim 2, wherein changing node assignment involves manual interaction by a user of the computer in response to hints provided by the computer.

5. The invention of claim 1, wherein generating the mapping includes:

packing circuit elements of a circuit design into blocks, each block corresponding to a CLB; and

generating the mapping by assigning the blocks to the CLBs in the PLD.

6. The invention of claim 5, wherein the mapping is generated using simulated annealing.

7. The invention of claim 1, wherein, for changing node assignment, the at least one node comprises a plurality of circuit elements.

8. The invention of claim 1, wherein:

selecting the critical path comprises;

identifying K critical paths in the PLD, where K>

1; and

selecting a most critical path of the K critical paths; and

the method further comprises;

selecting a new most critical path from K updated critical paths corresponding to the change in node assignment; and

changing node assignment for the new most critical path.

9. The invention of claim 1, wherein the different location falls within an area adjacent to the current location.

10. The invention of claim 9, wherein the node is a terminal node and the area is a circle centered at a connecting node and having a radius corresponding to a distance measure between the terminal and connecting nodes.

11. The invention of claim 10, wherein the distance measure is the Manhattan distance between the terminal and connecting nodes.

12. The invention of claim 9, wherein:

the node is an intermediate node; and

the area is an ellipse having the foci at two connecting nodes.

13. The invention of claim 1, wherein the change of circuit performance includes at least one of:

(i) change of one or more delays corresponding to one or more different paths having the reassigned node; and

(ii) size change of a bounding box for at least one net having the reassigned node.

14. The invention of claim 1, wherein changing node assignment includes at least one of:

(1) swapping two similar nodes between two locations;

(2) moving a node into an unassigned area of a new location; and

(3) swapping two dissimilar nodes between two locations.

15. A circuit mapping generated by implementing a method of mapping a plurality of circuit elements onto a plurality of configurable logic blocks (CLBs) in a programmable logic device (PLD), the method comprising:

generating an initial mapping of the circuit elements to the CLBs in the PLD;

selecting a critical path in the PLD corresponding to the initial mapping; and

for at least one node of the critical path, changing node assignment from a current location to a different location based on change of circuit performance corresponding to the change in node assignment.

16. A programmed PLD having a plurality of circuit elements mapped onto a plurality of CLBs, the PLD generated by implementing a method comprising:

generating a mapping of the circuit elements to the CLBs in the PLD;

selecting a critical path in the PLD corresponding to the mapping; and

for at least one node of the critical path, changing node assignment from a current location to a different location based on change of circuit performance corresponding to the change in node assignment.

17. A machine-readable medium, having encoded thereon program code, wherein, when the program code is executed by a machine, the machine implements a method of mapping a plurality of circuit elements onto a plurality of configurable logic blocks (CLBs) in a programmable logic device (PLD), the method comprising:

generating a mapping of the circuit elements to the CLBs in the PLD;

selecting a critical path in the PLD corresponding to the mapping; and

for at least one node of the critical path, changing node assignment from a current location to a different location based on change of circuit performance corresponding to the change in node assignment.

18. The invention of claim 17, wherein generating the mapping includes:

packing circuit elements of a circuit design into blocks, each block corresponding to a CLB; and

generating the mapping by assigning the blocks to the CLBs in the PLD.

19. The invention of claim 17, wherein:

selecting the critical path comprises;

identifying K critical paths in the PLD, where K>

1; and

selecting a most critical path of the K critical paths; and

the method further comprises;

selecting a new most critical path from K updated critical paths corresponding to the change in node assignment; and

changing node assignment for the new most critical path.

20. The invention of claim 17, wherein the different location falls within an area adjacent to the current location.

21. The invention of claim 20, wherein the node is a terminal node and the area is a circle centered at a connecting node and having a radius corresponding to a distance measure between the terminal and connecting nodes.

22. The invention of claim 20, wherein:

the node is an intermediate node; and

the area is an ellipse having the foci at two connecting nodes.

23. The invention of claim 17, wherein the change of circuit performance includes at least one, of:

(i) change of one or more delays corresponding to one or more different paths having the reassigned node; and

(ii) size change of a bounding box for at least one net having the reassigned node.