System and method for converting control flow graph representations to control-dataflow graph representations

• US 20040088689A1
• Filed: 10/31/2002
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Hammes, Jeffrey
• Granted Patent: US 7,299,458 B2
• Time in Patent Office: Days
• US Class Current: 717/154
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 8/447 Target code generation

Abstract

An embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, and converting said two or more basic blocks into code blocks, where the code blocks are formed into the control-dataflow graph. Another embodiment of the invention includes a method of forming a control-dataflow graph that includes separating a control flow graph into two or more basic blocks, forming a lode node in at least one of said basic blocks, forming a store node in at least one of said code blocks, inserting a delay node in at least one of said code blocks, segregating external hardware logic modules from said control flow graph, and converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

Claims

1. A method of forming a control-dataflow graph comprising:

separating a control flow graph into two or more basic blocks; and

converting said two or more basic blocks into code blocks, wherein the code blocks are formed into the control-dataflow graph.

2. The method of claim 1, comprising forming a lode node in at least one of said basic blocks.

3. The method of claim 1, comprising forming a store node in at least one of said code blocks.

4. The method of claim 1, comprising inserting a delay node in at least one of said code blocks.

5. The method of claim 1, comprising segregating external hardware logic modules from said control flow graph.