Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation

• US 20040088691A1
• Filed: 10/31/2002
• Published: 05/06/2004
• Est. Priority Date: 10/31/2002
• Status: Active Grant

• Current Assignee: FG SRC LLC (Freeman Capital Partners LP)
• Original Assignee: SRC Computers, Inc.
• Inventors: Poznanovic, Daniel, Hammes, Jeffrey, Gliem, Lonnie
• Granted Patent: US 7,155,708 B2
• Time in Patent Office: Days
• US Class Current: 717/158
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm. Another embodiment of the invention includes a method of simulating a control-dataflow graph that includes building an internal representation of the control-dataflow graph that includes one or more dataflow code blocks, and simulating the control-dataflow graph as a sequence of code block dataflow executions, where control is passed from one code block to another code block based on the output value of the code block until EXIT is reached.

Claims

1. A method of simulating a control-dataflow graph comprising:

building an internal representation of the control-dataflow graph comprising a current block;

sending a token the current block;

wherein said token executes the current block; and

producing an output value of the current block.

2. A method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a control-data flow emulator that emulates the reconfigurable logic for the algorithm.