Three-dimensional memory array and method of fabrication

• US 20040089917A1
• Filed: 10/20/2003
• Published: 05/13/2004
• Est. Priority Date: 04/28/2000
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Johnson, Mark, Knall, N. Johan
• Application Number:
  US10/689,187
• Publication Number:
  US 20040089917A1
• Time in Patent Office: Days
• US Class Current: 257/530
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 21/822 the substrate being a semiconductor, using silicon technology H01L21/8258 takes precedence
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence

Abstract

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally separated by an insulating layer used to form antifuses. In one embodiment, one-half the diode is located in one rail-stack and the other half in the other rail-stack.

Claims

1. A three dimensional multi-level memory array disposed above a substrate, the array comprising a plurality of memory cells, each memory cell comprising a silicon nitride antifuse.

2. The array of claim 1, further comprising p+n−

diodes or p−

n+ diodes.