Semiconductor device

• US 20040089936A1
• Filed: 11/07/2003
• Published: 05/13/2004
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Shizuno, Yoshinori
• Granted Patent: US 6,841,884 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06135 Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A semiconductor device includes a substrate having a chip mounting surface and a package surface. The semiconductor chip is mounted on the substrate and has electrode pads formed on a circuit forming surface thereof. The chip also has an insulating layer formed on the circuit forming surface and includes an opening for exposing the surface of electrode pads, conductive posts over the insulating layer, and re-distribution wirings formed on the insulating layer. The device has further has external terminals disposed on the package surface; substrate pads formed on the chip mounting surface, internal wirings formed on the chip mounting surface, and a sealing resin for sealing the chip mounting surface and the semiconductor chip.

Claims

1. A semiconductor device comprising:

a substrate having a chip mounting surface and a package surface;

a semiconductor chip mounted on the chip mounting surface;

wherein the semiconductor chip includes;

a plurality of electrode pads formed on a circuit forming surface of the semiconductor chip,

an insulating layer which is formed on the circuit forming surface and which includes an opening for exposing a part of the surface of each electrode pad,

a plurality of conductive posts disposed over the insulating layer, and

re-distribution wirings formed on the insulating layer to electrically connect the conductive posts to the electrode pads, external terminals disposed on the package surface;

substrate pads formed on the chip mounting surface so as to correspond the conductive posts;

internal wirings formed on the chip mounting surface to electrically connect the substrate pads and the external terminals; and

a sealing resin for sealing the chip mounting surface and the semiconductor chip.

2. The semiconductor device according to claim 1, wherein the interval between the conductive posts is wider than that between electrode pads, and the interval between the external terminals is wider than that between the conductive posts.

3. The semiconductor device according to claim 1, wherein a back surface of the semiconductor chip is exposed.

4. The semiconductor device according to claim 1, wherein the external terminals comprise solder balls.

5. A semiconductor device

a substrate having a chip mounting surface and a package surface;

a first semiconductor chip mounted on the chip mounting surface;

wherein the first semiconductor chip includes;

a plurality of first electrode pads formed on a first circuit forming surface of the first semiconductor chip,

an insulating layer which is formed on the first circuit forming surface and which includes an opening for exposing a part of the surface of each first electrode pad,

a plurality of conductive posts disposed over the insulating layer, and

re-distribution wirings formed on the insulating layer to electrically connect the conductive posts to the first electrode pads,

a second semiconductor chip mounted on a back surface of the first semiconductor chip and having a plurality of second electrode pads formed on a second circuit forming surface of the second semiconductor chip;

external terminals provided on the package surface;

substrate pads formed on the chip mounting surface so as to correspond the conductive posts;

bonding posts formed on the chip mounting surface;

bonding wires for connecting the second electrode pads to the bonding posts;

internal wirings formed on the chip mounting surface for electrically connecting the substrate pads and the bonding posts to the external terminals; and

a sealing resin for sealing the chip mounting surface, the bonding wires, and the first and second semiconductor chips.

6. The semiconductor device according to claim 5, wherein the interval between the conductive posts is wider than that between first electrode pads, and the interval between the external terminals is wider than that between the conductive posts.

7. The semiconductor device according to claim 5, wherein the external terminals comprise solder balls.

8. A semiconductor device comprising:

a substrate having a first surface and a second surface opposed to the first surface;

a semiconductor chip having a third surface and a fourth surface opposed to the third surface, and mounted on the first surface;

wherein the semiconductor chip includes;

a plurality of electrode pads formed on the third surface,

an insulating layer which is formed on the third surface and which includes an opening for exposing a part of the surface of each electrode pad,

a plurality of bump electrodes disposed over the insulating layer, and

wirings formed on the insulating layer to electrically connect the bump electrodes to the electrode pads,

external terminals disposed on the second surface;

substrate pads formed on the first surface;

conductive traces formed on the first surface to electrically connect the substrate pads and the external terminals; and

a sealing resin for sealing the first surface and the semiconductor chip.

9. The semiconductor device according to claim 8, wherein the interval between the bump electrodes is wider than that between electrode pads, and the interval between the external terminals is wider than that between the bump electrodes.

10. The semiconductor device according to claim 8, wherein the fourth surface of the semiconductor chip is exposed.

11. The semiconductor device according to claim 8, wherein the external terminals comprise solder balls.

12. A semiconductor device

a substrate having a first surface and a second surface opposed to the first surface;

a first semiconductor chip having a third surface and a fourth surface opposed to the third surface, and mounted on the first surface;

wherein the first semiconductor chip includes;

a plurality of first electrode pads formed on the third surface,

an insulating layer which is formed on the third surface and which includes an opening for exposing a part of the surface of each first electrode pad,

a plurality of bump electrodes disposed over the insulating layer, and

wirings formed on the insulating layer to electrically connect the bump electrodes to the first electrode pads,

a second semiconductor chip having a fifth surface and a sixth surface opposed to the fifth surface and having a plurality of second electrode pads formed on the fifth surface, the sixth surface being mounted on the fourth surface;

external terminals provided on the second surface;

substrate pads formed on the first surface;

bonding pads formed on the first surface;

bonding wires for connecting the second electrode pads to the bonding terminals;

conductive traces formed on the first surface for electrically connecting the substrate pads and the bonding pads to the external terminals; and

a sealing resin for sealing the first surface, the bonding wires, and the first and second semiconductor chips.

13. The semiconductor device according to claim 12, wherein the interval between the bump electrodes is wider than that between first electrode pads, and the interval between the external terminals is wider than that between the bump electrodes.

14. The semiconductor device according to claim 12, wherein the external terminals comprise solder balls.