Loop current monitor circuitry and method for a communication system

• US 20040091100A1
• Filed: 06/30/2003
• Published: 05/13/2004
• Est. Priority Date: 04/22/1997
• Status: Active Grant

• Current Assignee: Silicon Laboratories Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Scott, Jeffrey W., Krone, Andrew W., Welland, David R., Sooch, Navdeep S.
• Granted Patent: US 6,959,083 B2
• Time in Patent Office: Days
• US Class Current: 379/413
• CPC Class Codes: H04L 25/0266 Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
• CPC Class Codes: H04L 25/06 Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04M 1/573 Line monitoring circuits for detecting caller identification
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
• CPC Class Codes: H04M 19/001 Current supply source at the exchanger providing current to substations
• CPC Class Codes: H04M 19/02 providing ringing current or supervisory tones, e.g. dialling tone or busy tone
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A CMOS implementation for a DC holding circuit in direct access arrangement (DAA) circuitry is disclosed that provides desirable inductive behavior while minimizing power dissipation required by the CMOS integrated circuit, particularly at high loop currents. The DC holding circuitry disclosed may include MOS transistors located on a CMOS integrated circuit and an off-chip power dissipating resistor that acts to dissipate power external to the CMOS integrated circuit. The CMOS implementation disclosed also allows a path for drawing DC current to power other CMOS circuits (e.g., ADCs and DACs) in the CMOS integrated circuit.

Claims

1. A communication system, comprising:

phone line side circuitry that may be coupled to phone lines; and

a DC holding circuit within said phone line side circuitry including a power dissipating resistor coupled external to an integrated circuit chip interface of said phone line side circuitry.

2. The communication system of claim 1, further comprising powered side circuitry that may be coupled to said phone line side circuitry through an isolation barrier.

3. The communication system of claim 2, further comprising said isolation barrier coupled between said phone line side circuitry and said powered side circuitry.

4. The communication system of claim 3, wherein said isolation barrier comprises one or more capacitors.

5. The communication system of claim 2, wherein digital information is communicated across said isolation barrier.

6. The communication system of claim 1, wherein said DC holding circuitry comprises a MOS transistor and said power dissipating resistor is coupled within a current path of said MOS transistor.

7. A method for reducing power dissipation requirements for communication system, comprising:

coupling an isolation barrier between powered side circuitry and phone line side circuitry that may be coupled to phone lines;

providing a DC holding circuit within said phone line side circuitry that may be coupled to receive current from said phone lines; and

dissipating power within said DC holding circuit with a resistor that is coupled external to an integrated circuit chip interface of said phone line side circuitry.

8. The method of claim 7, wherein said isolation barrier is capacitive and digital information is transmitted across said isolation barrier.

9. The method of claim 7, wherein said dissipating step comprises positioning a MOS transistor within a current path of said DC holding circuit, generating an internal power supply to said integrated circuit, and coupling an external power dissipating resistor to said MOS transistor.

10. The method of claim 9, wherein said generating step comprises coupling a first voltage supply to a positive input terminal of an operational amplifier and a second voltage supply to a negative input terminal of said operational amplifier.

11. A DC holding circuit for reducing power dissipation requirements of an integrated circuit within a communication system that may be connected to phone lines, comprising:

power supply circuitry within phone line side circuitry that may be connected to phone lines to provide an internal DC supply voltage for the integrated circuit; and

a power dissipating resistor coupled to said power supply circuitry and coupled external to said chip interface of the integrated circuit.

12. The DC holding circuit of claim 11, wherein said power supply circuitry comprises a MOS transistor and wherein said power dissipating resistor is connected within a current path of said MOS transistor and outside of a current path of said internal DC supply voltage.

13. The DC holding circuit of claim 12, wherein said power supply circuitry further comprises a first and a second voltage supplies and an operational amplifier.

14. A method for reducing power dissipation requirements for an integrated circuit within a communication system that may be connected to phone lines, comprising:

providing a DC holding circuit that may receive current from phone lines;

generating an internal DC supply voltage for the integrated circuit with said DC holding circuit; and

coupling an external power dissipating resistor to said power supply circuitry and connected external to said chip interface of the integrated circuit.

15. The method of claim 14, wherein said coupling step further comprises positioning said power dissipating resistor outside of a current path for said internal DC supply voltage.

16. The method of claim 14, wherein said generating step includes providing a first and a second voltage supplies.