SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

• US 20040092063A1
• Filed: 05/27/2003
• Published: 05/13/2004
• Est. Priority Date: 11/12/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Furuta, Haruo, Ueno, Shuichi, Okumura, Yoshinori
• Granted Patent: US 6,770,522 B2
• Time in Patent Office: Days
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device and a manufacturing method thereof which is suited for forming both a transistor for a memory cell and a transistor for a high voltage circuit part on one semiconductor substrate, and moreover, has little deterioration of an electrical characteristic in the structure that a sidewall insulating film in a shared contact plug part is removed is provided. An active layer (16) is formed by performing an additional impurity injection on a part where a sidewall insulating film is removed in a forming portion of a shared contact plug (18a). An insulating film is laminated in a high voltage circuit part (AR1) and a sidewall insulating film (10d) of wide width is formed. According to this, a forming width of a sidewall insulating film (10a) can be made small in a MOS transistor for a memory cell part (AR2), and a forming width of a sidewall insulating film (10d) can be made large in a MOS transistor for a high voltage circuit part. Thereupon, in the high voltage circuit part (AR1), a source/drain active layer can be formed in the position more distant from a gate electrode.

Claims

1. A manufacturing method of a semiconductor device, comprising steps of:

(a) forming a conductive film on a semiconductor substrate;

(b) patterning said conductive film by a photolithography technique and an etching technique;

(c) forming a first active layer by performing an impurity injection in proximity of said patterned conductive film in a surface of said semiconductor substrate;

(d) forming an interlayer insulating film on a surface of said semiconductor substrate;

(e) forming a contact hole in which both said first active layer and said conductive film are exposed in said interlayer insulating film by a photolithography technique and an etching technique; and

(f) forming a second active layer by performing an impurity injection on a surface of said semiconductor substrate which is exposed in said contact hole.

2. The manufacturing method of the semiconductor device according to claim 1, further comprising a step of

(g) forming a sidewall insulating film on a side of said conductive film after said step (b) before said step (c), wherein

in said step (c), said first active layer is formed by performing an impurity injection with said sidewall insulating film and said conductive film as masks and

in said step (e), furthermore, said sidewall insulating film which is exposed in said contact hole is removed.