Method and apparatus for high throughput short packet transfers with minimum memory footprint

• US 20040093441A1
• Filed: 10/31/2003
• Published: 05/13/2004
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Brian A. Leete
• Original Assignee: Brian A. Leete
• Inventors: Leete, Brian A.
• Granted Patent: US 7,266,621 B2
• Time in Patent Office: Days
• US Class Current: 710/36
• CPC Class Codes: G06F 13/36 for access to common bus or bus system

Abstract

A device is presented including a host controller. A host controller driver is connected to the host controller. The host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order. Also presented is a method including determining whether execution of a first queue element transfer descriptor (qTD) in a first bank including many qTDs results in a short packet condition. Following an alternate pointer in the first bank that points to a second bank if execution of the first qTD resulted in the short packet condition. Following a next pointer to a second qTD in the first bank if the execution of the first qTD completed normally. Also executing the second qTD in the first bank. The qTDs in the first bank and the second bank are circularly linked.

Claims

1. An apparatus comprising:

a host controller; and

a host controller driver,

wherein a plurality of banks containing a plurality of queue element transfer descriptors (qTDs) are created for a plurality of buffers posted to the host controller driver, and the qTDs are circularly linked.

2. The apparatus of claim 1, wherein the host controller is an enhanced host controller interface (EHCI) host controller.

3. The apparatus of claim 1, wherein the banks are associated with a particular buffer in the plurality of buffers.

4. The apparatus of claim 3, wherein the plurality of buffers are ordered in an incremented order.

5. The apparatus of claim 4, wherein a second buffer is executed upon an occurrence of a short packet in a first qTD associated with a first buffer, the first qTD having an alternate next pointer pointing to a first qTD of the second buffer.

6. The apparatus of claim 1, wherein a next pointer in each of the plurality of qTDs in a first bank point to a next qTD in the first bank, a last qTD in the first bank points to a first qTD in the first bank.

7. An apparatus comprising:

a host controller; and

a host controller driver coupled to the host controller,

wherein the host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order.

8. The apparatus of claim 7, wherein a plurality of banks containing a plurality of qTDs are created for a plurality of buffers posted to the host controller driver.

9. The apparatus of claim 7, wherein the host controller is an enhanced host controller interface (EHCI) host controller.

10. The apparatus of claim 8, wherein the banks are associated with a particular buffer in the plurality of buffers.

11. The apparatus of claim 10, wherein a second buffer is executed upon an occurrence of a short packet in a first qTD associated with a first buffer, the first qTD having an alternate next pointer pointing to a first qTD of the second buffer.

12. The apparatus of claim 8, wherein a next pointer in each of the plurality of qTDs in a first bank point to a next qTD in the first bank, a last qTD in the first bank points to a first qTD in the first bank.

13. A system comprising:

a bus;

a first host controller coupled to the bus; and

a second host controller coupled to the first host controller;

wherein the first host controller arranges queue element transfer descriptors (qTDs) in a circularly linked order.

14. The system of claim 13, wherein a plurality of banks containing a plurality of qTDs are created for a plurality of buffers posted to a host controller driver.

15. The system of claim 13, wherein the first host controller is an enhanced host controller interface (EHCI) host controller.

16. The system of claim 14, wherein the banks are associated with a particular buffer in the plurality of buffers.

17. The system of claim 16, wherein a second buffer is executed upon an occurrence of a short packet in a first qTD associated with a first buffer, the first qTD having an alternate next pointer pointing to a first qTD of the second buffer.

18. The system of claim 13, wherein a next pointer in each of the plurality of qTDs in a first bank point to a next qTD in the first bank, a last qTD in the first bank points to a first qTD in the first bank.