High-performance, superscalar-based computer system with out-of-order instruction execution

• US 20040093482A1
• Filed: 11/05/2003
• Published: 05/13/2004
• Est. Priority Date: 07/08/1991
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hagiwara, Yasuki, Wang, Johannes, Wang, Sze-Shun, Miyayama, Yoshiyuki, Trang, Quang H., Lau, Te-Li, Garg, Sanjiv, Lentz, Derek J., Nguyen, Le-Trong
• Granted Patent: US 6,941,447 B2
• Time in Patent Office: Days
• US Class Current: 712/214
• CPC Class Codes: G06F 9/30061 Multi-way branch instructions, e.g. CASE
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/327 for interrupts
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3806 using address prediction, e.g. return stack, branch history buffer
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/384 Register renaming
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3856 Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3863 : using multiple copies of the architectural state, e.g. shadow registers
• CPC Class Codes: G06F 9/3865 : using deferred exception handling, e.g. exception flags
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

Claims

1. A microprocessor for executing instructions obtained from an instruction store, said microprocessor comprising:

a) means for fetching instruction sets from an instruction store, each instruction set including an instruction;

b) means, coupled to said fetching means, for buffering instruction sets, said buffering means including a first buffer and a second buffer; and

c) means, coupled to said first and second buffers, for executing instructions, said executing means including register file means for storing data in a plurality of registers, a plurality of functional unit means for processing data wherein each said functional unit means processes data in a predetermined manner, bus means for providing plural data routing paths between said register file means and said plurality of functional unit means, and means for controlling the execution of instructions.

2. The microprocessor of claim 1 wherein said controlling means is coupled to said first and second buffers for examining the instructions within the instruction sets buffered therein, said controlling means including means for selecting an instruction to be executed, means for selecting instruction determined ones of said plurality of registers for the transfer of data and instruction determined ones of said plurality of functional unit means for the processing of data.

3. The microprocessor of claim 2 wherein said controlling means directs the operation of said bus means to transfer data between said instruction determined one of said plurality of registers and said instruction determined ones of said plurality of functional unit means.

4. The microprocessor of claim 1, 2, or 3 wherein said controlling means provides for the concurrent execution of instructions, said controlling means controlling the initiation of the execution of instructions based on the availability of said functional unit means for the processing of data.

5. A microprocessor comprising:

a) means for obtaining a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference;

b) means for storing respective data in a plurality of registers including a predetermined register and a temporary register; and

c) means, coupled to said obtaining means, for sequentially executing said predetermined sequence of instructions, said executing means including means for directing the storage of data by an a-sequentially executed instruction to said temporary register where the register referenced by said a-sequentially executed instruction is said predetermined register.

6. A microprocessor comprising:

a) means for storing data in a plurality of registers identifiable by register references, said plurality of registers including a predetermined register and a temporary register;

b) means for obtaining a predetermined sequence of instructions to be executed, wherein an instruction of said predetermined sequence of instructions includes a register reference;

c) executing means, coupled to said obtaining means, for a-sequentially executing said predetermined sequence of instructions, said executing means including means, coupled to said storing means, for selecting saied temporary register where the sequential execution of said instruction provides said register reference to select said predetermined register for the storage of data.

7. The microprocessor of claim 6 wherein said executing means further includes means for determining whether all instructions in said predetermined sequence of instructions prior to said instruction have been executed and means, responsive to said determining means and coupled to said storing means, for transferring the data stored by said temporary register to said predetermined register.