Method for monitoring a microprocessor and circuit arrangement having a microprocessor

• US 20040093508A1
• Filed: 08/04/2003
• Published: 05/13/2004
• Est. Priority Date: 08/03/2002
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Foerstner, Dirk, Schier, Johannes
• Granted Patent: US 7,287,198 B2
• Time in Patent Office: Days
• US Class Current: 726/34
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs

Abstract

A method for monitoring a microprocessor and a circuit arrangement having a microprocessor are described. A microprocessor is monitored using an assigned watchdog. The watchdog monitors whether reset pulses are received within a time interval of predetermined duration. If the reset pulse is received, the time interval is reset and restarted. If reset pulses are not received, a reset of the microprocessor is initiated. In suitable operating phases of the microprocessor, a check function of the watchdog is activated. During the execution of the check function, first a reset of the watchdog is executed and then a sequence of waiting loops, whose duration is greater than the duration of the time interval of the watchdog, is executed.

Claims

1. A method for monitoring a microprocessor using an assigned watchdog, comprising:

causing the watchdog to monitor a reception of a reset pulse within a time interval of a predetermined duration;

causing the watchdog to initiate a reset of the microprocessor if the reset pulse is not received; and

executing at least one check function of the watchdog in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein a duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval.

2. The method as recited in claim 1, further comprising:

generating an error message if the watchdog has not reset the microprocessor by an end of the sequence of waiting loops.

3. The method as recited in claim 1, further comprising:

incrementing a counter with the execution of the at least one check function, the execution of the at least one check function being a function of a content of the counter.

4. The method as recited in claim 3, further comprising:

performing the at least one check function at the content of the counter; and

skipping the at least one check function at another content of the counter, the counter alternating between the content of the counter and the other content of the counter.

5. The method as recited in claim 3, wherein:

the counter has four counter contents,

an analysis is performed at one of the four counter contents, and

the least one check function is executed each time at the other counter contents.

6. The method as recited in claim 5, wherein:

a variable of the at least one check function corresponding to the duration of the sequence of waiting loops, is changed as a function of the counter content by changing a number of waiting loops contained in the sequence.

7. The method as recited in claim 6, wherein:

the duration of the sequence of waiting loops is reduced with each subsequent execution of the at least one check function, the duration being less than the time interval of the watchdog during the last execution, before the at least one check function is skipped.

8. The method as recited in claim 1, wherein:

a number of waiting loops in the sequence of waiting loops is selected during at least one execution of the at least one check function in such a way that the duration of the execution of the sequence of waiting loops is less than the time interval gives a clock rate that is slightly above an upper tolerance limit.

9. The method as recited in claim 1, wherein:

the operating phase is at least a switching on of the microprocessor.

10. The method as recited in claim 1, wherein:

the watchdog is supplied a clock signal that differs from a clock signal of the microprocessor.

11. A circuit arrangement, comprising:

a counter;

a microprocessor;

a watchdog assigned to the microprocessor and for performing a reset of the microprocessor if a reset pulse is not received within a time interval of predetermined duration, wherein;

a different clock signal is supplied to the watchdog than to the microprocessor; and

a non-volatile memory to which is assigned the microprocessor, at least a counter content of the counter being stored in the non-volatile memory.

12. The circuit arrangement as recited in claim 11, wherein:

the non-volatile memory includes an EEPROM.

13. The circuit arrangement as recited in claim 11, wherein:

the non-volatile memory is a part of the microprocessor.

14. A memory component storing a computer program that when executed on a microprocessor results in a performance of the following:

causing a watchdog to monitor a reception of a reset pulse within a time interval of a predetermined duration;

causing the watchdog to initiate a reset of the microprocessor if the reset pulse is not received; and

executing at least one check function of the watchdog in an operating phase of the microprocessor, each one of the at least one check function including a reset of the watchdog and an execution of a sequence of waiting loops, wherein a duration of the execution of the sequence of waiting loops of at least one of the at least one check function is greater than the predetermined duration of the time interval.