Tri-gate devices and methods of fabrication
First Claim
Patent Images
1. A semiconductor device comprising:
- a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate film;
a gate dielectric formed on said top surface of said silicon body and on said laterally opposite sidewalls of said silicon body; and
a gate electrode formed on said gate dielectric on said top of surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said silicon body.
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Abstract
The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.
240 Citations
51 Claims
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1. A semiconductor device comprising:
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a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate film;
a gate dielectric formed on said top surface of said silicon body and on said laterally opposite sidewalls of said silicon body; and
a gate electrode formed on said gate dielectric on said top of surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said silicon body. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A tri-gate transistor comprising:
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a single crystalline silicon body formed on an insulating substrate, said silicon body having a top surface and first and second laterally opposite sidewalls;
a gate dielectric formed on said top surface of said silicon body and on said first and second laterally opposite sidewalls of said silicon body;
a gate electrode formed on said gate dielectric on said top surface of said silicon body and adjacent to said gate dielectric on said first and said second laterally opposite sidewalls of said silicon body; and
a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode. - View Dependent Claims (9, 10, 11, 12, 13, 14, 16, 17)
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15. The tri-gate transistor of 14 wherein said single crystalline silicon body is doped to a first conductivity type with a concentration of 1×
- 1016-1×
1018 atoms/cm3. - View Dependent Claims (18)
- 1016-1×
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19. A transistor comprising:
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a plurality of semiconductor bodies each having a top surface and a pair of laterally opposite sidewalls formed on a substrate film;
a gate dielectric formed on the top surface and sidewalls of each of said semiconductor bodies;
a gate electrode formed on the gate dielectric on the top surface of each of said plurality of semiconductor bodies and adjacent to said gate dielectrics formed on each of said first and second laterally opposite sidewalls of each of said silicon bodies; and
a pair of source/drain regions formed in each of said semiconductor bodies on opposite sides of said gate electrode. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A fully depleted semiconductor on insulator transistor comprising:
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a silicon body formed on an insulating film;
a gate dielectric formed on and around said silicon body;
a gate electrode formed on said gate dielectric on and around said silicon body;
a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrodes;
wherein said gate length of said transistor is less than or equal to the width of said silicon body; and
when said transistor is turned “
ON”
said silicon body between said source/drain regions is fully depleted - View Dependent Claims (26, 27, 28, 29, 30, 31)
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32. A fully depleted silicon on insulator transistor comprising:
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a silicon body formed on an insulating substrate;
a gate dielectric formed on and around said silicon body;
a gate electrode formed on and adjacent to said gate dielectric formed on and around said silicon body;
a pair of source/drain regions formed on opposite sides of said gate electrode in said silicon body; and
wherein said transistor has a very sharp sub-threshold slope of less than 80 mV/decade and a drain induced barrier lowering of less than 100 mV/V. - View Dependent Claims (33, 34)
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35. A method of forming a semiconductor device comprising:
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forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate film;
forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body; and
forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body. - View Dependent Claims (36, 37, 38, 39, 40, 41, 42)
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43. A method of forming a silicon on insulator transistor comprising:
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patterning a silicon film formed on an insulating substrate into a silicon body having a top surface opposite a bottom surface formed on said insulating film, and a first and second laterally opposite sidewalls;
forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body;
depositing a gate material over said silicon body and over said insulating substrate;
patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to the laterally opposite sidewalls of said silicon body; and
forming a pair of source/drain regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51)
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Specification