Tri-gate devices and methods of fabrication

• US 20040094807A1
• Filed: 11/07/2003
• Published: 05/20/2004
• Est. Priority Date: 08/23/2002
• Status: Active Grant

• Current Assignee: Brian S. Doyle, Douglas Barlage, Jack Kavalieros, Robert S. Chau, Suman Datta
• Original Assignee: Brian S. Doyle, Douglas Barlage, Jack Kavalieros, Robert S. Chau, Suman Datta
• Inventors: Chau, Robert S., Kavalieros, Jack, Doyle, Brian S., Datta, Suman, Barlage, Douglas
• Granted Patent: US 7,504,678 B2
• Time in Patent Office: Days
• US Class Current: 257/401
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: H01L 29/0665 the shape of the body defining a nanostructure nanotechnology per se B82B
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners
• CPC Class Codes: H01L 29/78645 with multiple gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/482 the IGFET comprising multiple separately-addressable gate electrodes
• CPC Class Codes: H10K 85/221 Carbon nanotubes
• CPC Class Codes: Y10S 977/742 Carbon nanotubes, CNTs
• CPC Class Codes: Y10S 977/842 for carbon nanotubes or fullerenes
• CPC Class Codes: Y10S 977/938 Field effect transistors, FETS, with nanowire- or nanotube-channel region

Abstract

The present invention is a semiconductor device comprising a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer is formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body.

Claims

1. A semiconductor device comprising:

a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate film;

a gate dielectric formed on said top surface of said silicon body and on said laterally opposite sidewalls of said silicon body; and

a gate electrode formed on said gate dielectric on said top of surface of said semiconductor body and adjacent to said gate dielectric on said laterally opposite sidewalls of said silicon body.

2. The device of claim 1 wherein said semiconductor body is silicon.

3. The device of claim 1 wherein said semiconductor body is a single crystalline film.

4. The device of claim 2 wherein said semiconductor body is intrinsic single crystalline silicon.

5. The device of claim 1 wherein said semiconductor body is a semiconductor selected from the group consisting of silicon (Si) germanium (Ge), silicon germanium (Si_xGe_y), gallium arsenide (GaAs), InSb, GaP, GaSb as well as carbon nanotubes.

6. The semiconductor device of claim 1 wherein said substrate is an insulating substrate.

7. The semiconductor of claim 1 wherein said substrate is a semiconductor substrate.

8. A tri-gate transistor comprising:

a single crystalline silicon body formed on an insulating substrate, said silicon body having a top surface and first and second laterally opposite sidewalls;

a gate dielectric formed on said top surface of said silicon body and on said first and second laterally opposite sidewalls of said silicon body;

a gate electrode formed on said gate dielectric on said top surface of said silicon body and adjacent to said gate dielectric on said first and said second laterally opposite sidewalls of said silicon body; and

a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrode.

9. The tri-gate transistor of claim 8 wherein said transistor has a gate length (Lg) approximately equal to the distance between said first and second laterally opposite sidewalls of said silicon body.

10. The tri-gate transistor of claim 8 wherein said transistor has a gate length (Lg) approximately equal to the distance from said insulating film to the top surface of said silicon body.

11. The tri-gate transistor of claim 8 wherein the distance between said laterally opposite sidewalls of said silicon body is approximately equal to the distance from said insulating substrate to the top surface of said silicon body.

12. The trigate transistor of claim 8 wherein the distance between said laterally opposite sidewalls of said semiconductor is between ½

to two times the thickness of said silicon body on said insulating surface.

13. The tri-gate transistor of claim 8 wherein said single crystalline silicon body is intrinsic silicon.

14. The tri-gate transistor of claim 8 wherein said single crystalline silicon body is doped to a first conductivity type with a concentration of between 1×

10¹⁶-1×

10²⁰ atoms/cm³.

16. The tri-gate transistor of claim 8 further comprising a pair of sidewall spacer formed along laterally opposite sidewalls of said gate electrode.

17. The tri-gate transistor of claim 8 wherein said pair of source/drain regions further comprise silicon formed on and around said silicon body.

15. The tri-gate transistor of 14 wherein said single crystalline silicon body is doped to a first conductivity type with a concentration of 1×

10¹⁶-1×

10¹⁸ atoms/cm³.

18. The tri-gate transistor of claim 15 wherein said silicon on said source/drain regions is epitaxial silicon.

19. A transistor comprising:

a plurality of semiconductor bodies each having a top surface and a pair of laterally opposite sidewalls formed on a substrate film;

a gate dielectric formed on the top surface and sidewalls of each of said semiconductor bodies;

a gate electrode formed on the gate dielectric on the top surface of each of said plurality of semiconductor bodies and adjacent to said gate dielectrics formed on each of said first and second laterally opposite sidewalls of each of said silicon bodies; and

a pair of source/drain regions formed in each of said semiconductor bodies on opposite sides of said gate electrode.

20. The transistor of claim 19 wherein said gate width of said transistor is approximately the sum of the gate widths of each of said semiconductor bodies wherein the gate width of a semiconductor body is two times the height of the semiconductor body plus the distances between the laterally opposite sidewalls.

21. The tri-gate transistor of claim 19 wherein the distance between the laterally opposite sidewalls of each of said silicon bodies is approximately the same.

22. The transistor of claim 19 wherein each of said source regions are coupled together and each of said drain regions are coupled together.

23. The transistor of claim 19 wherein said substrate is an insulating substrate.

24. The transistor of claim 19 wherein said substrate is a semiconductor substrate.

25. A fully depleted semiconductor on insulator transistor comprising:

a silicon body formed on an insulating film;

a gate dielectric formed on and around said silicon body;

a gate electrode formed on said gate dielectric on and around said silicon body;

a pair of source/drain regions formed in said silicon body on opposite sides of said gate electrodes;

wherein said gate length of said transistor is less than or equal to the width of said silicon body; and

when said transistor is turned “

ON”

said silicon body between said source/drain regions is fully depleted

26. The transistor of claim 25 wherein said gate length is less than 60 nanometers

27. The transistor of claim 25 wherein said gate length is less than 30 nanometers.

28. The transistor of claim 25 wherein said gate length is less than 20 nanometers.

29. The transistor of claim 25 wherein said gate length is less than or equal to the height of said semiconductor body on said insulating film.

30. The transistor of claim 25 wherein said semiconductor body is a single crystalline silicon film.

31. The transistor of claim 30 wherein said single crystralline silicon film is intrinsic silicon.

32. A fully depleted silicon on insulator transistor comprising:

a silicon body formed on an insulating substrate;

a gate dielectric formed on and around said silicon body;

a gate electrode formed on and adjacent to said gate dielectric formed on and around said silicon body;

a pair of source/drain regions formed on opposite sides of said gate electrode in said silicon body; and

wherein said transistor has a very sharp sub-threshold slope of less than 80 mV/decade and a drain induced barrier lowering of less than 100 mV/V.

33. The transistor of claim 32 wherein said drain induced barrier lowering is less than 80 mV/V.

34. The transistor of claim 32 wherein said sub-threshold slope is about 60 mV/decade.

35. A method of forming a semiconductor device comprising:

forming a semiconductor body having a top surface and laterally opposite sidewalls on a substrate film;

forming a gate dielectric on said top surface of said semiconductor body and on said laterally opposite sidewalls of said semiconductor body; and

forming a gate electrode on said gate dielectric and adjacent to said gate dielectric on said laterally opposite sidewalls of said semiconductor body.

36. The device of claim 35 wherein said semiconductor body comprises single crystalline silicon.

37. The device of claim 36 wherein said single crystalline silicon body is intrinsic silicon.

38. The device of claim 35 wherein said semiconductor body is selected from the group consisting of silicon (Si) germanium (Ge), silicon germanium (Si_xGe_y), gallium arsenide (GaAs), InSb, GaP, GaSb as well as carbon nanotubes.

39. The method of forming the device of claim 35 wherein the thickness of said semiconductor body from said insulating film to said semiconductor body top surface is approximately equal to the distance between said laterally opposite sidewalls of said silicon body.

40. The method of claim 35 wherein the thickness of said silicon body from said insulating layer to said top surface is between two times to ½

the distance between the laterally opposite sidewalls.

41. The method of claim 35 wherein said substrate is an insulating substrate.

42. The method of claims 35 wherein said substrate is a semiconductor substrate.

43. A method of forming a silicon on insulator transistor comprising:

patterning a silicon film formed on an insulating substrate into a silicon body having a top surface opposite a bottom surface formed on said insulating film, and a first and second laterally opposite sidewalls;

forming a gate dielectric layer on said top surface of said silicon body and on said sidewalls of said silicon body;

depositing a gate material over said silicon body and over said insulating substrate;

patterning said gate material to form a gate electrode on said gate dielectric layer on said top surface of said silicon body and adjacent to said gate dielectric on said sidewalls of said silicon body, said gate electrode having laterally opposite sidewalls which run perpendicular to the laterally opposite sidewalls of said silicon body; and

forming a pair of source/drain regions in said silicon body on opposite sides of said laterally opposite sidewalls of said gate electrode.

44. The method of claim 43 wherein said distance between said laterally opposite sidewalls of said silicon body is approximately equal to the thickness of said silicon body on said insulating substrate.

45. The method of claim 43 wherein the distance between said laterally opposite sidewalls of said gate electrode (gate length) is less than or equal to the distance between laterally opposite sidewalls of said silicon body.

46. The method of claim 43 wherein the distance between said laterally opposite sidewalls of said gate electrode (gate length) is less than or equal to the thickness of said silicon body on said insulating film.

47. The method of claim 43 wherein said silicon film is single crystalline silicon.

48. The method of claim 47 wherein said single crystalline silicon film is intrinsic silicon.

49. The method of claim 43 further comprising forming a pair of sidewall spacers on opposite sides of laterally opposite sidewalls of said gate electrode;

and

forming a silicon film on and around said silicon body and adjacent to said sidewall spacers.

50. The method of claim 43 further comprising forming a suicide on said silicon film formed on said silicon body.

51. The method of claim 43 wherein said silicon film is formed by a selective deposition process.