Wiring structure on semiconductor substrate and method of fabricating the same

• US 20040094841A1
• Filed: 11/03/2003
• Published: 05/20/2004
• Est. Priority Date: 11/08/2002
• Status: Active Grant

• Current Assignee: AOI Electronics Company Limited
• Original Assignee: Casio Computer Company Limited
• Inventors: Arai, Kazuyoshi, Matsuzaki, Tomio
• Granted Patent: US 7,285,867 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A semiconductor device includes a semiconductor substrate having a plurality of connecting pads on one surface, an insulating film formed on one surface of the semiconductor substrate. The insulating film has holes each corresponding to one of the connecting pads, and a recess having a bottom surface depressed from the upper surface in the direction of thickness. Interconnections are formed on an upper surface of the insulating film or on the bottom surface of the recess, and connected to the connecting pads through the holes in the insulating film.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a plurality of connecting pads on one surface;

an insulating film formed on one surface of the semiconductor substrate, and having holes each corresponding to one of the connecting pads, an upper surface, and a recess having a bottom surface depressed from the upper surface in a direction of thickness; and

interconnections formed on the upper surface of the insulating film or on the bottom surface of the recess, and connected to the connecting pads through the holes in the insulating film.

2. A device according to claim 1, wherein each of the interconnections is formed on the bottom surface of the recess in the insulating film.

3. A device according to claim 1, wherein each of the recesses in the insulating film has a pair of side surfaces, and spaces are defined between each interconnection and the side surfaces of the recess.

4. A device according to claim 1, wherein the interconnections have connecting pad portions, and which further comprises bump electrodes formed on the connecting pad portions, and an encapsulating film formed between the bump electrodes on the insulating film including the interconnections.

5. A device according to claim 4, further comprising an upper insulating film formed between the insulating film and encapsulating film, and having holes formed in portions corresponding to the bump electrodes.

6. A device according to claim 5, wherein the insulating film and upper insulating film are made of materials containing the same main component.

7. A device according to claim 5, wherein the upper insulating film and encapsulating film are made of different materials.

8. A device according to claim 4, wherein each of the bump electrodes protrudes from an upper surface of the encapsulating film.

9. A device according to claim 4, wherein each of the bump electrodes has a lower bump electrode and upper bump electrode formed thereon.

10. A device according to claim 9, wherein the lower bump electrode protrudes from the upper surface of the encapsulating film.

11. A device according to claim 1, wherein the interconnections have connecting pad portions formed on the connecting pads, and which further comprises bump electrodes formed on the connecting pad portions, and an encapsulating film formed between the bump electrodes on the insulating film.

12. A device according to claim 1, wherein the insulating film is made of an organic resin.

13. A device according to claim 1, wherein the recess in the insulating film has a depth not less than a thickness of the interconnection.

14. A device according to claim 1, wherein the insulating film has a thickness of 10 to 30 μ

m.

15. A device according to claim 1, wherein the recess has a depth of 5 to 15 μ

m.

16. A device according to claim 15, wherein the insulating film has a thickness of not less than 1 μ

m from the bottom surface of the recess.

17. A device according to claim 1, wherein the interconnections are formed on the upper surface of the insulating film.

18. A device according to claim 17, wherein the recess in the insulating film has a width substantially the same as intervals between the interconnections.

19. A device according to claim 17, wherein the interconnections have connecting pad portions, and which further comprises bump electrodes formed on the connecting pad portions, and an encapsulating film formed between the bump electrodes on the insulating film including the interconnections.

20. A device according to claim 19, which further comprises an upper insulating film formed between the insulating film and encapsulating film, and holes formed in portions corresponding to the bump electrodes.

21. A device according to claim 20, wherein the insulating film and upper insulating film are made of materials containing the same main component.

22. A device according to claim 20, wherein the upper insulating film and encapsulating film are made of different materials.

23. A semiconductor device fabrication method comprising:

preparing a semiconductor substrate having a plurality of connecting pads on one surface;

forming, on one surface of the semiconductor substrate, an insulating film having holes each corresponding to one of the connecting pads, an upper surface, and a recess having a bottom surface depressed from the upper surface in a direction of thickness; and

forming, on the upper surface of the insulating film or on the bottom surface of the recess, interconnections connected to the connecting pads through the holes in the insulating film.

24. A method according to claim 23, wherein the interconnections are formed on the bottom surface of the recess.

25. A method according to claim 23, wherein the recess is formed to have a depth substantially equal to or larger than a thickness of the interconnection.

26. A method according to claim 23, further comprising forming connecting pad portions on the interconnections, forming bump electrodes on the connecting pad portions of the interconnections, and forming an encapsulating film between the bump electrodes on the upper surface of the insulating film including the interconnections.

27. A method according to claim 26, further comprising forming a solder ball on an upper surface of each bump electrode.

28. A method according to claim 26, further comprising forming, between the insulating film and encapsulating film, an upper insulating film having holes formed in portions corresponding to the bump electrodes.

29. A method according to claim 26, wherein the bump electrodes are formed to protrude from an upper surface of the encapsulating film.

30. A method according to claim 29, wherein each bump electrode has a lower bump electrode and upper bump electrode.

31. A method according to claim 26, further comprising forming, on the insulating film, connecting lines connected to the interconnections.

32. A method according to claim 31, further comprising forming lower bump electrodes by electroplating so as to be leveled with the encapsulating film, and forming upper bump electrodes on the lower bum electrodes by electroplating by using the connecting lines as plating current paths.

33. A method according to claim 23, wherein the interconnections are formed on the upper surface of the insulating film.

34. A method according to claim 33, wherein after the interconnections are formed on the upper surface of the insulating film, the recess is formed in the insulating film.

35. A method according to claim 34, wherein the recess is formed by etching by using the interconnections as masks.