RF MEMS switch matrix

• US 20040095205A1
• Filed: 04/03/2003
• Published: 05/20/2004
• Est. Priority Date: 11/14/2002
• Status: Active Grant

• Current Assignee: HRL Laboratories LLC (The Boeing Co.)
• Original Assignee: HRL Laboratories LLC (The Boeing Co.)
• Inventors: Schaffner, James H., Loo, Robert Y.
• Granted Patent: US 6,888,420 B2
• Time in Patent Office: Days
• US Class Current: 333/101
• CPC Class Codes: H01H 59/0009 making use of micromechanics
• CPC Class Codes: H01H 67/22 Switches without multi-position wipers
• CPC Class Codes: H01P 1/127 Strip line switches

Abstract

A broadband multiple input, multiple output switch matrix. The switch matrix comprises multiple crosspoint switch element tiles. Each tile comprises RF MEMS switches disposed on a substrate to provide a crosspoint switching capability. The crosspoint switch element tiles are disposed in a flip-chip manner on the upper side of an RF substrate that provides RF connectivity between the various crosspoint switch element tiles. A bias line substrate disposed on the lower side of the RF substrate receives control signals for the crosspoint switch element tiles and routes the signals through the RF substrate using vias in the RF substrate.

Claims

1. A switch element tile comprising:

a substrate;

a first switch disposed on said substrate, the first switch operable to electrically connect a row input to a row output;

a second switch disposed on said substrate, the second switch operable to electrically connect a column input to a column output; and

a third switch disposed on said substrate, the third switch operable to electrically connect the row input to the column output.

2. The switch element tile of claim 1, wherein at least one switch of the group consisting of the first switch, the second switch, and the third switch is a radio frequency (RF) micro electromechanical system (MEMS) switch.

3. The switch element tile of claim 1 further comprising:

a first pair of actuation bias pads disposed on said substrate, said first pair of actuation bias pads coupled to said first switch to provide a control signal to selectably switch said first switch;

a second pair of actuation bias pads disposed on said substrate, said second pair of actuation bias pads coupled to said second switch to provide a control signal to selectably switch said second switch; and

a third pair of actuation bias pads disposed on said substrate, said third pair of actuation bias pads coupled to said third switch to provide a control signal to selectably switch said third switch.

4. The switch element tile of claim 1 further comprising:

a first switch element microstrip line disposed on said substrate, said first switch element microstrip line having a first input segment electrically coupled to said row input and having a first output segment electrically coupled to said row output, said first switch operable to electrically connect said first input segment to said first output segment;

a second switch element microstrip line disposed on said substrate, said second switch element microstrip line having a second input segment electrically coupled to said column input and having a second output segment electrically coupled to said column output, said second switch operable to electrically connect said second input segment to said second output segment, said second switch element microstrip line being electrically isolated from said first switch element microstrip line; and

a third switch element microstrip line disposed on said substrate, said third switch element microstrip line having a third input segment electrically coupled to said row input and having a third output segment electrically coupled to said column output, said third switch operable to electrically connect said third input segment to said third output segment.

5. The switch element tile of claim 4, wherein said second switch element microstrip line further comprises an airbridge to provide electrical isolation from said first switch element microstrip line.

6. The switch element tile of claim 5, wherein said airbridge is fabricated using microwave monolithic integrated circuit techniques.

7. The switch element tile of claim 5, wherein said airbridge is formed by assembling said switch element tile on a second substrate, said second substrate having at least one microstrip line providing electrical continuity within said second switch element microstrip line.

8. The switch element tile of claim 4 further comprising:

a first microstrip branch disposed on said substrate, said first microstrip branch being electrically coupled to said row input, said first input segment and said third input segment; and

a second microstrip branch disposed on said substrate, said second microstrip branch being electrically coupled to said column output, said second output segment and said third output segment.

9. The switch element tile of claim 1, further comprising:

a row input pad disposed on said substrate, said row input pad coupled to said row input;

a row output pad disposed on said substrate, said row output pad coupled to said row output;

a column input pad disposed on said substrate, said column input pad coupled to said column input;

a column output pad disposed on said substrate, said column output pad coupled to said column output; and

one or more solder bumps disposed on at least one pad of the group of pads consisting of said row input pad, said row output pad, said column input pad, and said column output pad.

10. The switch element tile of claim 1 wherein said substrate has an upper surface and a lower surface, said first switch, said second switch, and said third switch are disposed on said upper surface and said lower surface is metallized.

11. The switch element tile of claim 2, wherein said MEMS switch is an electro-statically actuated MEMS switch.

12. The switch element of claim 1, wherein at least one switch of the group consisting of the first switch, the second switch, and the third switch comprises a field effect transistor or a PIN diode.

15. The switch matrix according to claim 4, wherein at least one switch element tile comprises:

a substrate;

a first MEMS switch to switchably couple said row input to said row output;

a second MEMS switch to switchably couple said column input to said column output; and

a third MEMS switch to switchably couple said row input to said column output,

wherein said first MEMS switch, said second MEMS switch, and said third MEMS switch are disposed on said substrate.

16. The switch matrix according to claim 15, wherein said at least one switch element tile further comprises:

a first pair of actuation bias pads disposed on said substrate, said first pair of actuation bias pads coupled to said first switch to provide a control signal to selectably switch said first MEMS switch;

a second pair of actuation bias pads disposed on said substrate, said second pair of actuation bias pads coupled to said second switch to provide a control signal to selectably switch said second MEMS switch; and

a third pair of actuation bias pads disposed on said substrate, said third pair of actuation bias pads coupled to said third switch to provide a control signal to selectably switch said third MEMS switch.

17. The switch matrix according to claim 15, wherein said at least one switch element tile further comprises:

a first switch element microstrip line disposed on said substrate, said first switch element microstrip line having a first input segment electrically coupled to said row input and having a first output segment electrically coupled to said row output, said first switch operable to electrically connect said first input segment to said first output segment;

a second switch element microstrip line disposed on said substrate, said second switch element microstrip line having a second input segment electrically coupled to said column input and having a second output segment electrically coupled to said column output, said second switch operable to electrically connect said second input segment to said second output segment, said second switch element microstrip line being electrically isolated from said first switch element microstrip line; and

a third switch element microstrip line disposed on said substrate, said third switch element microstrip line having a third input segment electrically coupled to said row input and having a third output segment electrically coupled to said column output, said third switch operable to electrically connect said third input segment to said third output segment.

18. The switch matrix according to claim 17, wherein said second switch element microstrip line further comprises an airbridge to provide electrical isolation from said first switch element microstrip line.

19. The switch matrix according to claim 18, wherein said airbridge is fabricated using microwave monolithic integrated circuit techniques.

20. The switch matrix according to claim 18, wherein said airbridge comprises at least one microstrip line disposed on said RF substrate layer, said microstrip line providing electrical continuity within said second switch element microstrip line.

21. The switch matrix according to claim 15, wherein said at least one switch element tile further comprises:

a first microstrip branch disposed on said substrate, said first microstrip branch being electrically coupled to said row input, said first input segment and said third input segment; and

a second microstrip branch disposed on said substrate, said second microstrip branch being electrically coupled to said column output, said second output segment and said third output segment.

22. The switch matrix of claim 15, wherein said at least one switch element tile further comprises:

a row input pad disposed on said substrate, said row input pad coupled to said row input;

a row output pad disposed on said substrate, said row output pad coupled to said row output;

a column input pad disposed on said substrate, said column input pad coupled to said column input;

a column output pad disposed on said substrate, said column output pad coupled to said column output; and

one or more solder bumps disposed on at least one pad of the group of pads consisting of said row input pad, said row output pad, said column input pad, and said column output pad.

13. A switch matrix for switching any one of multiple signal inputs to any one of multiple signal outputs, said switch matrix comprising:

an array of switch element tiles, each switch element tile having one or more switch element inputs and one or more switch element outputs, each switch element tile of said array being disposed to couple at least one switch element output of each switch element tile to a switch element input of an adjacent switch element tile or to one signal output of said multiple signal outputs;

a radio frequency (RF) substrate layer on which said array of switch element tiles is disposed, said RF substrate layer coupling each one of said multiple signal inputs to a corresponding switch element input, said RF substrate layer coupling each one of said multiple signal outputs to a corresponding switch element output, and said RF substrate layer coupling said at least one switch element output of each switch element tile to said switch element input of said adjacent switch element tile; and

a bias line substrate layer on which said RF substrate layer is disposed, said bias line substrate layer having a plurality of switch element control inputs, said bias line substrate layer directing said switch element control inputs to said switch element tiles.

14. The switch matrix according to claim 13, wherein the array of switch element tiles are arranged in rows and columns and the one or more switch element inputs of each switch element tile comprise a row input and a column input and the one or more switch element outputs of each switch element tile comprise a row output and a column output and each switch element tile operates to switchably couple said row input to said row output or said column output and to switchably couple said column input to said column output or said row output.

23. The switch matrix according to claim 13, wherein said RF substrate layer has an upper RF substrate surface and a lower RF substrate surface, said RF substrate layer comprising:

a plurality of bias vias extending from said lower RF substrate surface to said upper RF substrate surface, said plurality of bias vias electrically connecting said plurality of switch element control inputs to said switch element tiles; and

a plurality of microstrip lines, selected ones of said microstrip lines electrically connecting each output of each switch element tile to an input of an adjacent switch element tile or to a signal output of said multiple signal outputs.

24. The switch matrix according to claim 23, wherein said bias line substrate layer comprises:

a plurality of bias line solder pads, each bias line solder pad being disposed to electrically contact a corresponding bias via; and

a plurality of bias lines, each bias line electrically connected to at least one bias line solder pad,

wherein said switch element control inputs are applied to one or more bias lines of said plurality of bias lines.

25. The switch matrix according to claim 13, wherein said RF substrate layer or said bias line layer comprise multiple layers fabricated using multiple layer circuit board techniques.

26. The switch matrix according to claim 13, wherein said RF substrate layer and said bias line layer comprise a multiple layer motherboard fabricated using multiple layer circuit board techniques.

27. The switch matrix according to claim 14, wherein microstrip lines disposed on said RF substrate layer couple row outputs of at least a portion of said plurality of switch element tiles to row inputs of adjacent switch element tiles and microstrip lines disposed on said RF substrate layer couple column outputs on at least a portion of said plurality of switch element tiles to column inputs of adjacent switch element tiles.

28. The switch matrix according to claim 27, wherein the row output of each switch element tile not coupled to the row input of an adjacent switch element tile or to one of said multiple signal outputs is coupled to a chip terminator, the column output of each switch element tile not coupled to the column input of an adjacent switch element tile or to one of said multiple signal outputs is coupled to a chip terminator, the row input of each switch element tile not coupled to the row output of an adjacent switch element tile or to one of said multiple signal inputs is coupled to a chip terminator, and the column input of each switch element tile not coupled to the column output of an adjacent switch element tile or to one of said multiple signal inputs is coupled to a chip terminator.

29. A method for connecting various ones of M inputs to various ones of N outputs comprising the steps of:

providing a plurality of crosspoint switch tiles, each crosspoint switch tile having a row input, a column input, a row output, and a column output and each crosspoint switch tile being switchably operable to couple said row input to said row output or said column output and to couple said column input to said row output or said column output;

disposing said plurality of crosspoint switch tiles on an upper side of a radio frequency (RF) substrate, said upper side of said RF substrate having a plurality of microstrip lines;

arranging said plurality of crosspoint switch tiles on said RF substrate in rows and columns, wherein the row input of each crosspoint switch tile in each row is electrically coupled to the row output of an adjacent crosspoint switch tile in the same row or to one input of said M inputs with at least one microstrip line of said plurality of microstrip lines and the column output of each crosspoint switch tile in each column is coupled to the column input of an adjacent crosspoint switch tile or to one output of said N outputs with at least one microstrip line of said plurality of microstrip lines;

receiving crosspoint switch signals at a bias line substrate disposed on a lower side of said RF substrate; and

routing said crosspoint switch signals to said plurality of crosspoint switch tiles with control lines disposed on said bias line substrate and bias vias disposed within said RF substrate.

30. The method of claim 29 further comprising the steps of:

disposing at least one chip terminator at the row output of each crosspoint switch tile not electrically coupled to the row input of an adjacent crosspoint switch tile or to one output of said N outputs;

disposing at least one chip terminator at the column output of each crosspoint switch tile not electrically coupled to the column input of an adjacent crosspoint switch tile or to one output of said N outputs;

disposing at least one chip terminator at the row input of each crosspoint switch tile not electrically coupled to the row output of an adjacent crosspoint switch tile or to one input of said M inputs; and

disposing at least one chip terminator at the column input of each crosspoint switch tile not electrically coupled to the column output of an adjacent crosspoint switch tile or to one input of said M inputs.

31. The method of claim 29 wherein at least one crosspoint switch tile comprises:

a substrate;

a first MEMS switch disposed on said substrate, said first MEMS switch switchably coupling said row input to said row output;

a second MEMS switch disposed on said substrate, said second MEMS switch switchably coupling said column input to said column output; and

a third MEMS switch disposed on said substrate, said third MEMS switch switchably coupling said row input to said column output.

32. The method of claim 31 wherein said at least one crosspoint switch tile further comprises:

a first microstrip line disposed on said substrate, said microstrip line having a first input segment electrically coupled to said row input and having a first output segment electrically coupled to said row output, said first MEMS switch operable to electrically connect said first input segment to said first output segment;

a second microstrip line disposed on said substrate, said second microstrip line having a second input segment electrically coupled to said column input and having a second output segment electrically coupled to said column output, said second MEMS switch operable to electrically connect said second input segment to said second output segment, said second microstrip line being electrically isolated from said first microstrip line; and

a third microstrip line disposed on said substrate, said third microstrip line having a third input segment electrically coupled to said row input and having a third output segment electrically coupled to said column output, said third MEMS switch operable to electrically connect said third input segment to said third output segment.

33. The method of claim 32, wherein said second microstrip line further comprises an airbridge to provide electrical isolation from said first microstrip line.

34. The method of claim 33, wherein said airbridge is fabricated using microwave monolithic integrated circuit techniques.

35. The method of claim 33, wherein said airbridge comprises one or more microstrip lines disposed on said RF substrate.

36. The method of claim 32, wherein said at least one crosspoint switch tile further comprises:

a first microstrip branch disposed on said substrate, said first microstrip branch being electrically coupled to said row input, said first input segment and said third input segment; and

a second microstrip branch disposed on said substrate, said second microstrip branch being electrically coupled to said column output, said second output segment and said third output segment.

37. The method of claim 32, wherein said at least one crosspoint switch tile further comprises:

a row input pad disposed on said substrate, said row input pad coupled to said row input;

a row output pad disposed on said substrate, said row output pad coupled to said row output;

a column input pad disposed on said substrate, said column input pad coupled to said column input;

a column output pad disposed on said substrate, said column output pad coupled to said column output; and

one or more solder bumps disposed on at least one pad of the group of pads consisting of said row input pad, said row output pad, said column input pad, and said column output pad.

38. The method of claim 29, wherein said RF substrate or said bias line substrate comprise multiple layers fabricated using multiple layer circuit board techniques.

39. The method of claim 29, wherein said RF substrate and said bias line substrate comprise a multiple layer motherboard fabricated using multiple layer circuit board techniques.