Saving power in a GPS receiver by controlling domain clocking

• US 20040095272A1
• Filed: 11/18/2002
• Published: 05/20/2004
• Est. Priority Date: 11/18/2002
• Status: Abandoned Application

• Current Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Warloe, Andreas, Cox, Wayne
• Application Number:
  US10/298,415
• Publication Number:
  US 20040095272A1
• Time in Patent Office: Days
• US Class Current: 342/357.66
• CPC Class Codes: G01S 19/21 Interference related issues ; Issues related to cross-correlation, spoofing or other methods of denial of service
• CPC Class Codes: G01S 19/29 carrier including Doppler, related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption

Abstract

The controller of the present invention is incorporated in a global positioning system (GPS) receiver and operates to control the power consumed by the receiver by controlling the clocking of numerous domains. Each domain includes circuitry associated with different functions of the receiver. For example, the receiver of the present invention includes domains for each channel, where the channels are used to locate and track GPS signals. When one or more of the channels are not in use, the controller deactivates the clock signal to the one or more unused channels, thereby minimizing the power consumed by the receiver.

Claims

1. A GPS receiver comprising:

a domain adapted to receive a clock signal, wherein said domain corresponds to a portion of circuitry adapted to perform digital signal processing on a baseband digital representation of a received GPS signal; and

a controller adapted to provide said clock signal and control the power consumption of said domain by activating or deactivating said clock signal.

2. The GPS receiver of claim 1 further comprising a plurality of domains including said domain, wherein said plurality of domains corresponds to said circuitry adapted to perform said digital signal processing on said baseband digital representation of said received GPS signal.

3. The GPS receiver of claim 2 wherein said controller is further adapted to provide a plurality of clock signals including said clock signal and control the power consumption of said plurality of domains by activating or deactivating said plurality of clock signals.

4. The GPS receiver of claim 3 wherein at least two of said plurality of domains are selected from a group consisting of:

a) a channel domain adapted to receive one of said plurality of clock signals;

b) a transform domain adapted to receive one of said plurality of clock signals;

c) an integrated phase modulator domain adapted to receive one of said plurality of clock signals;

d) a data collect domain adapted to receive one of said plurality of clock signals;

e) an events domain adapted to receive one of said plurality of clock signals;

f) a user time logic domain adapted to receive one of said plurality of clock signals; and

g) a receiver circuitry domain adapted to receive one of said plurality of clock signals.

5. The GPS receiver of claim 3 wherein said plurality of domains comprise a plurality of GPS channel domains each adapted to receive one of said plurality of clock signals, wherein said controller is further adapted to deactivate said one of said plurality of clock signals when an associated channel domain is not in use.

6. The GPS receiver of claim 1 wherein said controller is further adapted to include a code and power management module adapted to activate or deactivate said clock signal.

7. The GPS receiver of claim 1 wherein said domain comprises a GPS channel domain adapted to receive said clock signal.

8. The GPS receiver of claim 1 wherein said domain comprises a transform domain adapted to receive said clock signal.

9. The GPS receiver of claim 1 wherein said domain comprises an integrated phase modulator domain adapted to receive said clock signal.

10. The GPS receiver of claim 1 wherein said domain comprises a data collect domain adapted to receive said clock signal.

11. The GPS receiver of claim 1 wherein said domain comprises an events domain adapted to receive said clock signal.

12. The GPS receiver of claim 1 wherein said domain comprises a user time logic domain adapted to receive said clock signal.

13. The GPS receiver of claim 1 wherein said domain comprises a receiver circuitry domain adapted to receive said clock signal.

14. The GPS receiver of claim 1 wherein said domain comprises circuitry implementing complementary metal-oxide-silicon technology, thereby being capable of minimizing power consumption when said clock signal is deactivated.