GPS receiver

• US 20040095274A1
• Filed: 11/18/2002
• Published: 05/20/2004
• Est. Priority Date: 11/18/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Imai, Benjamin, Warloe, Andreas, Najarian, Richard
• Granted Patent: US 6,778,135 B2
• Time in Patent Office: Days
• US Class Current: 342/357.63
• CPC Class Codes: G01S 19/215 issues related to spoofing
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/34 Power consumption
• CPC Class Codes: H04B 2201/70715 with application-specific features

Abstract

The global positioning system (GPS) receiver of the present invention operates to search a range of frequencies by correlating a baseband signal corresponding to a received GPS signal with a generated frequency and a generated code at a plurality of time offsets. Address translation logic operates to group results of the correlation according to the plurality of time offsets by translating addresses received from a direct memory access (DMA) controller in order to improve the efficiency of performing a fast Fourier transform (FFT) on the results of the correlation. The transformed data produced by the FFT process are used by the GPS receiver to determine a frequency of the received GPS signal and a time offset associated with a ranging code carried in the received GPS signal.

Claims

1. A GPS receiver comprising:

correlation circuitry adapted to provide data corresponding to a correlation of a signal with a plurality of generated signals;

control circuitry adapted to provide said plurality of generated signals to said correlation circuitry;

circuitry adapted to receive and store said data from said correlation circuitry; and

transform circuitry adapted to retrieve said data from said circuitry and transform said data into a frequency domain to produce transformed data, which is used by the GPS receiver to determine a frequency of said signal and a time offset associated with a ranging code carried in said signal.

2. The GPS receiver of claim 1 further comprising jammer response circuitry adapted to provide a control signal based on an occurrence of a transmission from an associated wireless communications device, wherein said correlation circuitry is further adapted to provide said data based on said control signal.

3. The GPS receiver of claim 2 wherein said correlation circuitry comprises accumulation circuitry adapted to accumulate results of said correlation based on said control signal to provide said data.

4. The GPS receiver of claim 3 wherein said accumulation circuitry is further adapted to stop accumulation of said correlation when said control signal is activated and resume accumulation when said control signal is deactivated.

5. The GPS receiver of claim 2 wherein said jammer response circuitry activates said control signal during said transmission and deactivates said control signal when said transmission is complete.

6. The GPS receiver of claim 1 wherein said plurality of generated signals comprises a generated frequency and a generated code at a plurality of time offsets.

7. The GPS receiver of claim 1 wherein said circuitry comprises:

memory adapted to store said data from said correlation circuitry in a plurality of memory locations corresponding to a plurality of translated addresses;

address translation logic adapted to provide said plurality of translated addresses each based on an address from memory access logic; and

said memory access logic adapted to provide each said address to said address translation logic.

8. The GPS receiver of claim 1 wherein said memory access logic comprises a direct memory access controller.

9. The GPS receiver of claim 1 further comprising a domain adapted to receive a clock signal, wherein said domain corresponds to a portion of digital signal processing circuitry adapted to process said signal and said controller is further adapted to provide said clock signal and control the power consumption of said domain by activating or deactivating said clock signal.

10. The GPS receiver of claim 9 further comprising a plurality of domains including said domain, wherein said plurality of domains corresponds to said digital signal processing circuitry.

11. The GPS receiver of claim 10 wherein said controller is further adapted to provide a plurality of clock signals including said clock signal and control the power consumption of said plurality of domains by activating or deactivating said plurality of clock signals.

12. A system incorporating a GPS receiver comprising:

a receiver frontend adapted to receive a GPS signal and provide a baseband signal based on said GPS signal;

correlation circuitry adapted to provide data corresponding to a correlation of said baseband signal with a plurality of generated signals;

control circuitry adapted to provide said plurality of generated signals to said correlation circuitry;

circuitry adapted to receive and store said data from said correlation circuitry; and

transform circuitry adapted to retrieve said data from said circuitry and transform said data into a frequency domain to produce transformed data, which is used by the GPS receiver to determine a frequency of said baseband signal and a time offset associated with a ranging code carried in said baseband signal.

13. The system of claim 12 further comprising a wireless communications device adapted to transmit a communications signal, wherein said communications signal is substantially stronger than said GPS signal.

14. The system of claim 13 further comprising jammer response circuitry adapted to provide a control signal based on an occurrence of a transmission of said communications signal from said wireless communications device, wherein said correlation circuitry is further adapted to provide said data based on said control signal.

15. The system of claim 14 wherein said correlation circuitry comprises accumulation circuitry adapted to accumulate results of said correlation based on said control signal to provide said data.

16. The system of claim 15 wherein said accumulation circuitry is further adapted to stop accumulation of said correlation when said control signal is activated and resume accumulation when said control signal is deactivated.

17. The system of claim 14 wherein said detection circuitry activates said control signal during said transmission and deactivates said control signal when said transmission is complete.

18. The system of claim 12 wherein said plurality of generated signals comprises a generated frequency and a generated code at a plurality of time offsets.

19. The system of claim 12 wherein said circuitry comprises:

memory adapted to store said data from said correlation circuitry in a plurality of memory locations corresponding to a plurality of translated addresses;

address translation logic adapted to provide said plurality of translated addresses each based on an address from memory access logic; and

said memory access logic adapted to provide each said address to said address translation logic.

20. The system of claim 12 wherein said memory access logic comprises a direct memory access controller.

21. The system of claim 12 further comprising a domain adapted to receive a clock signal, wherein said domain corresponds to a portion of digital signal processing circuitry adapted to process said signal and said controller is further adapted to provide said clock signal and control the power consumption of said domain by activating or deactivating said clock signal.

22. The system of claim 21 further comprising a plurality of domains including said domain, wherein said plurality of domains corresponds to said digital signal processing circuitry.

23. The system of claim 22 wherein said controller is further adapted to provide a plurality of clock signals including said clock signal and control power consumption of said plurality of domains by activating or deactivating said plurality of clock signals.