Array substrate for liquid crystal display device and method of manufacturing the same

• US 20040095544A1
• Filed: 11/12/2003
• Published: 05/20/2004
• Est. Priority Date: 11/11/2002
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Chang, Youn-Gyoung, Yoo, Soon-Sung, Cho, Heung-Lyul
• Granted Patent: US 7,016,007 B2
• Time in Patent Office: Days
• US Class Current: 349/152
• CPC Class Codes: G02F 1/134336 Matrix
• CPC Class Codes: G02F 1/13458 Terminal pads
• CPC Class Codes: G02F 1/1362 Active matrix addressed cells G02F1/134336, G02F1/134363 take precedence
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: G02F 1/136231 for reducing the number of lithographic steps
• CPC Class Codes: G02F 1/136236 using a grey or half tone lithographic process

Abstract

A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad and a gate electrode on a substrate through a first mask process, forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the substrate including the gate line, the gate pad and the gate electrode through a second mask process, wherein the data line crosses the gate line to define a pixel region, the source electrode is extended from the data line, the drain electrode is spaced apart from the source electrode, and the active layer is disposed between the gate electrode and the source and drain electrodes, forming a passivation layer on an entire surface of the substrate including the data line, the source electrode and the drain electrode through a third mask process, the passivation layer being etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad and the data pad, and forming a pixel electrode, a gate pad terminal and a data pad terminal by depositing a transparent conductive material on an entire surface of the substrate including the passivation layer, the pixel electrode directly contacting the exposed part of the drain electrode, the gate pad terminal directly contacting the gate pad, and the data pad terminal directly contacting the data pad.

Claims

1. An array substrate for a liquid crystal display device, comprising:

a gate line and a gate pad on a substrate;

a data line and a data pad on the substrate, the data line crossing the gate line to define a pixel region;

a thin film transistor at a crossing of the gate and data lines and including a gate electrode, an active layer, a source electrode and a drain electrode;

a passivation layer provided on an entire surface of the substrate including the thin film transistor, wherein the passivation layer is etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad, and the data pad; and

a pixel electrode, a gate pad terminal and a data pad terminal on the substrate including the passivation layer, the pixel electrode directly contacting the exposed part of the drain electrode, the gate pad terminal contacting the exposed gate pad, and the data pad terminal contacting the data pad.

2. The array substrate according to claim 1, wherein the passivation layer has reversely tapered sides.

3. The array substrate according to claim 1, wherein the passivation layer has a surface of a circular arc.

4. The array substrate according to claim 1, wherein the passivation layer is patterned, and the pixel electrode, the gate pad terminal and the data pad terminal are disposed between patterns of the passivation layer.

5. The array substrate according to claim 1, wherein the pixel electrode contacts the exposed substrate in the pixel region.

6. The array substrate according to claim 1, wherein an amorphous silicon layer and a doped amorphous silicon layer are layered under the data line and the data pad.

7. The array substrate according to claim 6, wherein edges of the amorphous silicon layer are exposed.

8. The array substrate according to claim 1, further comprising a metal pattern having an island shape over the gate line.

9. The array substrate according to claim 8, wherein the passivation layer further exposes a part of the metal pattern.

10. The array substrate according to claim 9, wherein the pixel electrode directly contacts the exposed part of the metal pattern, whereby the metal pattern forms a storage capacitor with the gate line.

11. The array substrate according to claim 1, further comprising a conductive pattern on the passivation layer, wherein the conductive pattern is made of the same material as the pixel electrode.

12. The array substrate according to claim 1, wherein the active layer has the same shape as the source and drain electrodes and also includes an additional portion between the source and drain electrodes.

13. The array substrate according to claim 1, further comprising an inorganic insulating pattern between the passivation layer and the thin film transistor, the gate line and the data line, wherein the inorganic insulating pattern has the same shape as the passivation layer.

14. A method of manufacturing an array substrate for a liquid crystal display device, comprising:

forming a gate line, a gate pad and a gate electrode on a substrate through a first mask process;

forming a data line, a data pad, a source electrode, a drain electrode and an active layer on the substrate including the gate line, the gate pad and the gate electrode through a second mask process, wherein the data line crosses the gate line to define a pixel region, the source electrode is extended from the data line, the drain electrode is spaced apart from the source electrode, and the active layer is disposed between the gate electrode and the source and drain electrodes;

forming a passivation layer over an entire surface of the substrate including the data line, the source electrode and the drain electrode through a third mask process, the passivation layer being etched to expose the substrate in the pixel region, a part of the drain electrode, the gate pad and the data pad; and

forming a pixel electrode, a gate pad terminal and a data pad terminal by depositing a transparent conductive material on an entire surface of the substrate including the passivation layer, the pixel electrode directly contacting the exposed part of the drain electrode, the gate pad terminal directly contacting the gate pad, and the data pad terminal directly contacting the data pad.

15. The method according to claim 14, wherein the second mask process including:

forming a gate insulating layer over the substrate including the gate line and the gate electrode;

depositing an amorphous silicon layer, a doped amorphous silicon layer and a metal layer over the gate insulating layer;

providing a photoresist pattern having first and second thicknesses over the metal layer;

selectively removing portions of the metal layer according to the photoresist pattern and selectively removing portions of the amorphous silicon layer according to the photoresist pattern;

removing a portion of the photoresist pattern having the second thickness;

selectively etching the metal layer exposed by removing the portion of the photoresist pattern having the second thickness;

selectively etching the doped amorphous silicon layer exposed by selectively etching the metal layer exposed by removing the photoresist pattern having the second thickness; and

removing the remaining photoresist pattern.

16. The method according to claim 15, wherein the photoresist pattern is a positive type such that a portion exposed to light is developed and removed.

17. The method according to claim 14, further comprising curing the passivation layer before forming the pixel electrode, whereby the passivation layer has reversely tapered sides having an angle smaller than 90 degrees.

18. The method according to claim 17, wherein the passivation layer has a surface of a circular arc.

19. The method according to claim 14, wherein an amorphous silicon layer and a doped amorphous silicon layer are formed under the data line and the data pad.

20. The method according to claim 19, wherein edges of the amorphous silicon layer are exposed.

21. The method according to claim 14, wherein a metal pattern having an island shape is formed over the gate line through the second mask process.

22. The method according to claim 21, wherein the passivation layer further exposes a part of the metal pattern.

23. The method according to claim 22, wherein the pixel electrode directly contacts the exposed part of the metal pattern, whereby the metal pattern forms a storage capacitor with the gate line and the gate insulating layer.

24. The method according to claim 14, wherein a mask of the second mask process includes a transmitting portion, a blocking portion, and a half transmitting portion.

25. The method according to claim 24, wherein the half transmitting portion includes slits.

26. The method according to claim 14, wherein the active layer has the same shape as the source electrode and the drain electrode and also includes an additional portion between the source and drain electrodes.

27. The method according to claim 14, further comprising forming an inorganic insulating layer on an entire surface of the substrate including the data line, the source electrode and the drain electrode, wherein the inorganic insulating layer is patterned by using the passivation layer as an etching mask, thereby forming an inorganic insulating pattern having the same shape as the passivation layer.

28. The method according to claim 27, further comprising removing the passivation layer after forming the pixel electrode, the gate pad terminal and the data pad terminal.

29. The method according to claim 28, wherein the passivation layer is removed using a liftoff method.