Digital filter of a mobile communication system and operating method thereof

• US 20040095951A1
• Filed: 09/03/2003
• Published: 05/20/2004
• Est. Priority Date: 10/30/2002
• Status: Abandoned Application

• Current Assignee: LG Nortel Company Limited
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Park, Won-Hyoung
• Application Number:
  US10/653,154
• Publication Number:
  US 20040095951A1
• Time in Patent Office: Days
• US Class Current: 370/437
• CPC Class Codes: H03H 17/0225 Measures concerning the multipliers
• CPC Class Codes: H03H 17/0275 comprising non-recursive filters
• CPC Class Codes: H03H 2218/06 Multiple-input, multiple-output [MIMO]; Multiple-input, single-output [MISO]

Abstract

A digital filter of a mobile communication system and an operating method thereof for processing digital signals inputted through plural channels: a first switch outputting digital signals, which are inputted through a plurality of channel paths, in a predetermined order with multiple rate; a filter unit processing signals inputted from the first switch in a poly-phase method; a second switch outputting output signals of the filter unit after dividing them by channels; and a clock unit for supplying clock signals to the first switch, the filter unit and the second switch. The digital filter of multi-channels can be integrated/miniaturized with one component and the filter processing rate can be improved.

Claims

1. A digital filter of a mobile communication system comprising:

a first switch outputting digital signals, which are inputted through a plurality of channel paths, in a predetermined order with multiple rate;

a filter unit processing signals inputted from the first switch in a poly-phase method;

a second switch outputting output signals of the filter unit after dividing them by channels; and

a clock unit supplying clock signals to the first switch, the filter unit and the second switch.

2. The filter of claim 1, wherein the first switch switches the digital signals, which are inputted from respective channels in certain rates, in a rate that multiplied by the number of channels.

3. The filter of claim 1, wherein the filter unit comprises a plurality of sub-filters as many as the number of the channels.

4. The filter of claim 3, wherein the sub-filter comprises:

a plurality of registers shifting the digital signals inputted from the first switch sequentially;

a plurality of multipliers for multiplying the signals inputted into respective channels of the registers by respective coefficients; and

an adder for adding output signals of the multipliers.

5. The filter of claim 1, wherein the second switch divides the digital signal outputted from the filter unit so that the channel of the signal is same as that of the digital signal inputted into the first switch.

6. The filter of claim 1, wherein the clock unit supplies multiple clock signals to the first switch, the filter unit and to the second switch.

7. A digital filter of a mobile communication system comprising:

a first switch interpolating and outputting digital signals inputted in channel unit through a plurality of channel paths in multiple rate;

a filter unit including a plurality of sub-filters processing digital signals inputted from the first switch in a poly-phase method;

a second switch re-arranging output signals of an adder by channels and outputting them; and

a clock unit supplying multiple clock signals to the first switch, the filter unit and the second switch.

8. The filter of claim 7, wherein the first switch switches digital signals inputted in ×

1 chip rate with a rate multiplied by the number of input channels.

9. The filter of claim 7, wherein the sub-filter comprises:

a plurality of registers for shifting repeatedly the digital signals inputted from the first switch;

a plurality of multipliers for multiplying the signals of channel unit inputted from the registers by corresponding coefficients; and

an adder for adding the output signals of the multipliers and outputting them.

10. The filter of claim 7, wherein the sub-filters are configured to have same structures.

11. A digital filter of a mobile communication system comprising:

a first switch interpolating digital signals inputted in ×

1 chip rate through a plurality of channels and outputting after arranging them in parallel sequentially;

a plurality of registers storing and shifting the digital signals inputted from the first switch;

a plurality of multipliers multiplying the signals inputted from the registers in respective channel unit by corresponding coefficients;

an adder for adding output signals of the multipliers;

a second switch re-arranging output signals of the adder by channels and outputting them; and

a clock unit supplying clock signals of N chip rate (N is 1 or larger natural number) in order to process the digital signals.

12. The filter of claim 11, wherein the shifting is repeatedly performed till the digital signal reaches to the last register.

13. The filter of claim 11, wherein the clock signal has a rate which is a plurality of times faster than that of the inputted digital signal.

14. An operating method of a digital filter in a mobile communication system processing digital signals inputted through a plurality of channels,

wherein the digital signal is filtered in a poly-phase method based on clock signals supplied in multiple rate.

15. The method of claim 14, wherein the clock signal has a multiple larger than the number of channels.

16. An operating method of a digital filter comprising:

inputting respective digital signals through a plurality of channels;

filtering the inputted digital signals in a poly-phase method; and

re-arranging the filtered digital signals by channels and outputting them.

17. The method of claim 16, wherein the step of inputting digital signals comprises:

interpolating the digital signals inputted through the respective channel paths by multiple clock signals; and

arranging the interpolated signals sequentially and outputting them.

18. The method of claim 16, wherein the step of filtering comprises:

repeatedly inputting the digital signal based on the multiple clock signals; and

multiplying the digital signals by certain coefficients when the digital signals as many as the number of channels are inputted and adding them.

19. An operating method of a digital filter comprising:

inputting digital signals into a first switch through a plurality of channels;

outputting the digital signals inputted by channels after interpolating the signals;

repeatedly inputting the interpolated digital signals in multiple rate to filter the signals in a poly-phase method; and

dividing the filtered digital signals by channels in a second switch and outputting them.

20. A digital filter of a mobile communication system comprising:

a first device outputting digital signals which are inputted through a plurality of channel paths, in a predetermined order with multiple rate;

a filter unit processing signals inputted from the first device in a poly-phase method;

a second device outputting output signals of the filter unit after dividing them by channels; and

a clock supplying clock signals to the first device, the filter unit and the second device.

21. A digital filter of a mobile communication system comprising:

a first device interpolating and outputting digital signals inputted in channel unit through a plurality of channel paths in multiple rate;

a filter unit including a plurality of sub-filters processing digital signals inputted from the first switch in a poly-phase method;

a second device re-arranging output signals of an adder by channels and ouptting them; and

a clock supplying multiple clock signals to the first device, the filter unit and the second device.

22. A digital filter of a mobile communication system comprising:

a first device interpolating digital signals inputted in ×

1 chip rate through a plurality of channels and outputting after arranging them in parallel sequentially;

a plurality of registers storing and shifting the digital signals inputted from the first switch;

a plurality of multipliers multiplying the signals inputted from the registers in respective channel unit by corresponding coefficients;

an adder for adding output signals of the multipliers;

a second device re-arranging output signals of the adder by channels and outputting them; and

a clock supplying clock signals of N chip rate (N is 1 or larger natural number) in order to process the digital signals.

23. An operating method of a digital filter comprising:

inputting digital signals into a first device through a plurality of channels;

outputting the digital signals inputted by channels after interpolating the signals;

repeatedly inputting the interpolated digital signals in multiple rate to filter the signals in a poly-phase method; and

dividing the filtered digital signals by channels in a second device and outputting them.