Encryption apparatus with parallel Data Encryption Standard (DES) structure

• US 20040096059A1
• Filed: 11/12/2003
• Published: 05/20/2004
• Est. Priority Date: 11/12/2002
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seo, Kyung-Duck
• Application Number:
  US10/706,829
• Publication Number:
  US 20040096059A1
• Time in Patent Office: Days
• US Class Current: 380/28
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0625 with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

Abstract

An encryption apparatus comprises first and second N-round DES devices and first and second input circuits. The first N-round DES device cryptographically converts a digital input data block into a first digital output data block nonlinearly, based on an input of a set of encryption keys. The first input means receives and inverts the digital input data block. The second input means receives and inverts the set of encryption keys. The second N-round DES device cryptographically converts the inverted digital input data block into a second digital output data block nonlinearly, based on an input of the inverted encryption keys. The first and second N-round DES devices perform a cryptographic conversion process at the same.

Claims

1. An encryption apparatus comprising:

a first N-round DES device for cryptographically converting a digital input data block into a first digital output data block nonlinearly, based on an input of a set of encryption keys;

a first input means for receiving and inverting the digital input data block;

a second input means for receiving and inverting the set of encryption keys; and

a second N-round DES device for cryptographically converting the inverted digital input data block into a second digital output data block nonlinearly, based on an input of the set of inverted encryption keys,

wherein the first and second N-round DES devices perform a substantially simultaneous cryptographic conversion process.

2. The encryption apparatus according to claim 1, wherein the first and second N-round DES devices perform a cryptographic conversion process according to a DES algorithm, respectively.

3. The encryption apparatus according to claim 1, further comprising means for storing the first and second digital output data blocks from the first and second N-round DES devices, either one of the first and second digital output data blocks being used as an encryption data block.

4. The encryption apparatus according to claim 1, further comprising a third input means for transferring the digital input data block to the first N-round DES device.

5. The encryption apparatus according to claim 1, further comprising an encryption key block for receiving a key and generating the set of encryption keys based on a permutation of the key.

6. The encryption apparatus according to claim 1, further comprising a fourth input means for transferring the set of encryption keys to the first N-round DES device.

7. A method of cryptographically converting digital input data comprising the steps of:

cryptographically converting a digital input data block into a first digital output data block nonlinearly, based on an input of a set of encryption keys;

inverting the digital input data block and the set of encryption keys; and

cryptographically converting the inverted digital input data block into a second digital output data block nonlinearly, based on an input of the inverted encryption keys, wherein the cryptographic conversion processes for obtaining the first and second digital output data blocks are substantially simultaneously performed according to a DES algorithm.

8. The method according to claim 7, wherein either one of the first and second digital output data blocks is used as an encryption data block.

9. An encryption apparatus having a substantially uniform current pattern during cryptographic processes comprising:

a first N-round DES device producing a first current pattern during cryptographic process on a digital input data block, based on an input of a set of encryption keys; and

a second N-round DES device producing a second current pattern during cryptographic process on an inverse of the digital input data block, based on an input of the set of inverted encryption keys,

wherein the first and second N-round DES devices perform a substantially simultaneous cryptographic conversion processes and wherein the first and second current patterns are inverse patterns, respectively.

10. The encryption apparatus according to claim 9, wherein the first and second N-round DES devices perform a cryptographic conversion process according to a DES algorithm, respectively.

11. The encryption apparatus according to claim 9, further comprising means for storing a first and second digital output data blocks from the first and second N-round DES devices, respectively, either one of the first and second digital output data blocks being used as an encryption data block.

12. The encryption apparatus according to claim 9, further comprising a third input means for transferring the digital input data block to the first N-round DES device.

13. The encryption apparatus according to claim 9, further comprising an encryption key block for receiving a key and generating the set of encryption keys based on a permutation of the key.

14. The encryption apparatus according to claim 9, further comprising a fourth input means for transferring the set of encryption keys to the first N-round DES device.