Wide dynamic range pinned photodiode active pixel sensor (aps)

• US 20040096124A1
• Filed: 11/15/2002
• Published: 05/20/2004
• Est. Priority Date: 11/15/2002
• Status: Active Grant

• Current Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Original Assignee: Aptina Imaging Corporation (ON Semiconductor Corporation)
• Inventors: Nakamura, Junichi
• Granted Patent: US 7,489,352 B2
• Time in Patent Office: Days
• US Class Current: 382/308
• CPC Class Codes: H04N 25/583 with different integration times
• CPC Class Codes: H04N 25/585 with pixels having different sensitivities within the sensor, e.g. fast or slow pixels or pixels having different sizes
• CPC Class Codes: H04N 25/778 comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself

Abstract

An image apparatus and method is disclosed for extending the dynamic range of an image sensor. A first linear pixel circuit produces a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period. A second linear pixel circuit produces a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, where the second integration period is shorter than the first integration period. A sample-and-hold circuit captures signals representing the first and second pixel output signals.

Claims

1. An imaging apparatus, comprising:

a first pixel circuit, comprising a first transfer pulse line, coupled to a gate of a first transfer transistor, wherein first transfer transistor transfers charge from a first photodiode to a first floating diffusion node, and wherein said first floating diffusion node is further coupled to a gate of a first source-follower transistor;

a second pixel circuit, comprising a second transfer pulse line, coupled to a gate of a second transfer transistor, wherein second transfer transistor transfers integrated charge from a second photodiode and to a second floating diffusion node, and wherein said second floating diffusion node is further coupled to a gate of a second source-follower transistor;

a reset pulse line, connected to the gate of a first and second reset transistor, wherein the first reset transistor is coupled to reset the first floating diffusion node to a predetermined voltage state, and the second reset transistor is coupled to reset the second floating diffusion node to a predetermined voltage state; and

a first and second row-select transistor, respectively coupled to the first and second source-follower transistors for respectively coupling said first and second source follower transistors to a first column signal line and a second column signal line, said first transfer pulse line receiving a signal which operates said first photodiode to integrate charge for a first time period and said second transfer pulse line receiving a signal which operates said second photodiode to integrate charge for a second time period different from said first time period.

2. The apparatus according to claims 1, wherein the first and second photodiodes are pinned photodiodes.

3. The apparatus according to claim 2, wherein the pinned photodiodes are coupled to ground.

4. The pixel circuit according to claim 1, further comprising a first capacitor coupled to a first floating diffusion node and a second capacitor coupled to the second floating diffusion node.

5. The pixel circuit according to claim 4, wherein the first and second capacitors are further coupled to ground.

6. An image apparatus, comprising:

a first linear pixel circuit for producing a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period;

a second linear pixel circuit for producing a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, wherein second integration period is shorter than the first integration period; and

a sample-and-hold circuit for capturing signals representing said first and second pixel output signals.

7. An apparatus as in claim 6, further comprising first and second column lines, respectively coupled to receive said signals representing said first and second pixel output signals.

8. An apparatus as in claim 7, wherein said sample-and-hold circuit comprises a first sample-and-hold circuit portion coupled to said first column line for capturing said signal representing said first pixel output signal and a second sample-and-hold circuit portion coupled to said second column line capturing said signal representing said second pixel output signal.

9. An apparatus as in claim 6, further comprising a column line commonly connected to receive said signal representing said first and second pixel output signals.

10. An apparatus as in claim 9, wherein said sample-and-hold circuit is coupled to said common column line and sequentially captures said signals representing said first and second pixel output signals.

11. An apparatus as in claim 9, further comprising an output transistor having a gate connected to receive said signals representing said first and second pixel output signals for providing a combined pixel output to said column line.

12. An apparatus as in claim 11, wherein said sample-and-hold circuit is coupled to said common column line and captures said combined pixel output signal.

13. An apparatus as in claim 6, wherein each of said first and second pixel circuits comprise a transfer transistor for transferring charge integrated by an associated photo-conversion device to an associated diffusion node.

14. An apparatus as in claim 13, wherein the transfer transistor of said first and second pixel circuit have respective gates for receiving respective transfer control signals which set the integration time for each pixel circuit.

15. An apparatus as in claim 6, wherein each said pixel circuit comprises:

a pinned photodiode as said photo-conversion device;

a diffusion node;

a transfer device, for transferring integrated charge from said photodiode to said diffusion node;

a reset device for resetting said diffusion node to a known state before said charge transfer; and

an output transistor having a gate connected to said diffusion node.

16. An apparatus as in claim 15, wherein each of said pixel circuits further comprises a row select transistor for selectively coupling an associated output transistor to a respective pixel output line, said sample and hold circuit having input portions respectively coupled to said pixel output line.

17. An apparatus as in claim 16, wherein the gates of said row select transistors are coupled together such that said signal representing said first and second pixel output signals are respectively output from said first and second pixel circuit to said respective output line.

18. A method for operating an image apparatus, comprising:

producing a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period;

producing a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, wherein second integration period is shorter than the first integration period; and

capturing signals representing said first and second pixel output signals.

19. A method as in claim 18, further comprising respectively transmitting said first and second pixel output signals to a first and second column line.

20. A method as in claim 19, wherein said act of capturing comprises capturing said first and second pixel output signals from said first and second column line.

21. A method as in claim 18, further comprising transmitting said first and second pixel output signals to a common column line.

22. A method as in claim 21, wherein said act of capturing comprises capturing said signals representing said first and second pixel output signals sequentially from said common line.

23. An imaging apparatus, comprising:

a first pixel circuit, comprising a first transfer pulse line, coupled to a gate of a first transfer transistor, wherein first transfer transistor transfers charge from a first photodiode to a floating diffusion node, and wherein said floating diffusion node is further coupled to a reset transistor and a gate of a source-follower transistor;

a second pixel circuit, comprising a second transfer pulse line, coupled to a gate of a second transfer transistor, wherein second transfer transistor transfers integrated charge from a second photodiode and to the floating diffusion node;

a reset pulse line, connected to the gate of the reset transistor, wherein the reset transistor is coupled to reset the floating diffusion node to a predetermined voltage state; and

a row-select transistor, respectively coupled to the source-follower transistors for respectively coupling said first and second pixel circuits to a column signal line, said first transfer pulse line receiving a signal which operates said first photodiode to integrate charge for a first time period and said second transfer pulse line receiving a signal which operates said second photodiode to integrate charge for a second time period different from said first time period.

24. The apparatus according to claim 23, wherein the first and second photodiodes are pinned photodiodes.

25. The apparatus according to claim 24, wherein the pinned photodiodes are coupled to ground.

26. The apparatus according to claim 23, further comprising a capacitor coupled to the floating diffusion node.

27. The apparatus according to claim 26, wherein the capacitor is further coupled to ground.

28. An imaging apparatus, comprising:

a first pixel circuit, comprising a first transfer pulse line, coupled to a gate of a first transfer transistor, wherein first transfer transistor transfers charge from a first photodiode to a first floating diffusion node, and wherein said first floating diffusion node is further coupled to a first reset transistor, a first capacitor, and a second capacitor, said second capacitor being coupled to a common floating gate line;

a second pixel circuit, comprising a second transfer pulse line, coupled to a gate of a first transfer transistor, wherein first transfer transistor transfers charge from a second photodiode to a second floating diffusion node, and wherein said second floating diffusion node is further coupled to a second reset transistor, a third capacitor, and a fourth capacitor, said fourth capacitor being coupled to the common floating gate line;

a reset pulse line, connected to the gates of the first and second reset transistor, wherein the first and second reset transistors are coupled to respectively reset the first and second floating diffusion node to a predetermined voltage state;

a floating gate pulse line, connected to a floating gate transistor, wherein the floating gate transistor is further coupled to the common floating gate line; and

a source-follower transistor, coupled to the common floating gate line for respectively coupling said first and second pixel circuits to a column signal line, said first transfer pulse line receiving a signal which operates said first photodiode to integrate charge for a first time period and said second transfer pulse line receiving a signal which operates said second photodiode to integrate charge for a second time period different from said first time period.

29. The apparatus according to claim 28, wherein the first and second photodiodes are pinned photodiodes.

30. The apparatus according to claim 29, wherein the pinned photodiodes are coupled to ground.

31. The apparatus according to claim 28, wherein a first thermal noise (kTC) voltage is transmitted and added to the floating gate line potential when the floating gate transistor is initially turned off.

32. The apparatus according to claim 31, wherein a second thermal noise (kTC) voltage is transmitted and added to the first and second floating diffusion node voltages when the first and second reset transistors are turned off, and wherein the first and second thermal noise voltages are added to a floating gate voltage present on the floating gate line to form a summed floating gate voltage.

33. The apparatus according to claim 32, wherein the summed floating gate voltage is sampled by a sample-and-hold circuit.

34. The apparatus according to claim 32, wherein the transferred charge from the first and second photodiode is added to the summed floating gate voltage.

35. The apparatus according to claim 28, wherein a floating gate threshold voltage is applied to the floating gate transistor.

36. The apparatus according to claim 35, wherein a source-follower threshold voltage is applied to the source-follower transistor.

37. The apparatus according to claim 36, wherein the floating gate threshold voltage is lower than the source-follower threshold voltage.

38. A processing system, comprising:

a processor; and

a CMOS imaging device, coupled to said processor, said imaging device comprising;

a first pixel circuit, comprising a first transfer pulse line, coupled to a gate of a first transfer transistor, wherein first transfer transistor transfers charge from a first photodiode to a first floating diffusion node, and wherein said first floating diffusion node is further coupled to a gate of a first source-follower transistor;

a second pixel circuit, comprising a second transfer pulse line, coupled to a gate of a second transfer transistor, wherein second transfer transistor transfers integrated charge from a second photodiode and to a second floating diffusion node, and wherein said second floating diffusion node is further coupled to a gate of a second source-follower transistor;

a reset pulse line, connected to the gate of a first and second reset transistor, wherein the first reset transistor is coupled to reset the first floating diffusion node to a predetermined voltage state, and the second reset transistor is coupled to reset the second floating diffusion node to a predetermined voltage state; and

a first and second row-select transistor, respectively coupled to the first and second source-follower transistors for respectively coupling said first and second source follower transistors to a first column signal line and a second column signal line, said first transfer pulse line receiving a signal which operates said first photodiode to integrate charge for a first time period and said second transfer pulse line receiving a signal which operates said second photodiode to integrate charge for a second time period different from said first time period.

39. The system according to claims 38, wherein the first and second photodiodes are pinned photodiodes.

40. The system according to claim 39, wherein the pinned photodiodes are coupled to ground.

41. The system according to claim 38, further comprising a first capacitor coupled to a first floating diffusion node and a second capacitor coupled to the second floating diffusion node.

42. The system according to claim 41, wherein the first and second capacitors are further coupled to ground.

43. A processing system, comprising:

a processor; and

a CMOS imaging device, coupled to said processor, said imaging device comprising;

a first linear pixel circuit for producing a first pixel output signal based on charge integration by a first photo-conversion device over a first integration period;

a second linear pixel circuit for producing a second pixel output signal based on charge integration by a second photo-conversion device over a second integration period, wherein second integration period is shorter than the first integration period; and

a sample-and-hold circuit for capturing signals representing said first and second pixel output signals.

44. An system as in claim 43, further comprising first and second column lines, respectively coupled to receive said signals representing said first and second pixel output signals.

45. An system as in claim 44, wherein said sample-and-hold circuit comprises a first sample-and-hold circuit portion coupled to said first column line for capturing said signal representing said first pixel output signal and a second sample-and-hold circuit portion coupled to said second column line capturing said signal representing said second pixel output signal.

46. An system as in claim 43, further comprising a column line commonly connected to receive said signal representing said first and second pixel output signals.

47. An system as in claim 46, wherein said sample-and-hold circuit is coupled to said common column line and sequentially captures said signals representing said first and second pixel output signals.

48. An system as in claim 46, further comprising an output transistor having a gate connected to receive said signals representing said first and second pixel output signals for providing a combined pixel output to said column line.

49. An system as in claim 48, wherein said sample-and-hold circuit is coupled to said common column line and captures said combined pixel output signal.

50. An system as in claim 43, wherein each of said first and second pixel circuits comprise a transfer transistor for transferring charge integrated by an associated photo-conversion device to an associated diffusion node.

51. A system as in claim 50, wherein the transfer transistor of said first and second pixel circuit have respective gates for receiving respective transfer control signals which set the integration time for each pixel circuit.